litex/migen/fhdl
Lars-Peter Clausen 72579a6129 Add support for negative slice indices
In python a negative indices usually mean start counting from the right side.
I.e. if the index is negative is acutal index used is len(l) + i. E.g. l[-2]
equals l[len(l)-2].

Being able to specify an index this way also comes in handy for migen slices in
some cases. E.g. the following snippet can be implement to shift an abitrary
length register n bits to the right:
	reg.eq(Cat(Replicate(0, n), reg[-n:])

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 21:56:01 +01:00
..
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00
autofragment.py fhdl/autofragment: bugfixes + add auto_attr 2013-03-03 17:53:06 +01:00
namer.py New 'specials' API 2013-02-22 17:56:35 +01:00
specials.py fhdl/specials: allow setting memory name 2013-02-25 23:14:03 +01:00
structure.py Add support for negative slice indices 2013-03-12 21:56:01 +01:00
tools.py fhdl/verilog: insert reset before listing signals 2013-02-27 18:10:04 +01:00
tracer.py fhdl/namer: better handling of indices 2012-09-09 19:33:55 +02:00
verilog.py fhdl/verilog: tristate outputs are always wire 2013-03-06 11:30:52 +01:00
visit.py fhdl: support nested statement lists 2013-01-05 14:18:15 +01:00