litex/lib/sata
Florent Kermarrec 3e5a4ab097 add wr_only and rd_only mode to BIST (to test speed) and switch to 100MHz system clock 2014-12-23 20:41:13 +01:00
..
command improve BIST and clean up (remove support of identify command and debug code) 2014-12-23 19:27:52 +01:00
link improve BIST and clean up (remove support of identify command and debug code) 2014-12-23 19:27:52 +01:00
phy use new submodules collection to expose more fsm an modules 2014-12-19 22:50:35 +01:00
test improve BIST and clean up (remove support of identify command and debug code) 2014-12-23 19:27:52 +01:00
transport add identify device to command_tb and revert endianness (seems conform with Lecroy SATA Protocol suite samples) 2014-12-20 13:26:07 +01:00
__init__.py improve BIST and clean up (remove support of identify command and debug code) 2014-12-23 19:27:52 +01:00
bist.py add wr_only and rd_only mode to BIST (to test speed) and switch to 100MHz system clock 2014-12-23 20:41:13 +01:00
common.py improve BIST and clean up (remove support of identify command and debug code) 2014-12-23 19:27:52 +01:00