170 lines
3.8 KiB
Python
170 lines
3.8 KiB
Python
from lib.sata.common import *
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from lib.sata.link.scrambler import Scrambler
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from migen.bank.description import *
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class SATABISTUnit(Module):
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def __init__(self, sata_con):
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sink = sata_con.source
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source = sata_con.sink
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self.start = Signal()
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self.write_only = Signal()
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self.read_only = Signal()
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self.sector = Signal(48)
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self.count = Signal(4)
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self.done = Signal()
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self.ctrl_errors = Signal(32)
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self.data_errors = Signal(32)
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self.counter = counter = Counter(bits_sign=32)
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self.ctrl_error_counter = Counter(self.ctrl_errors, bits_sign=32)
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self.data_error_counter = Counter(self.data_errors, bits_sign=32)
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self.scrambler = scrambler = InsertReset(Scrambler())
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self.comb += [
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scrambler.reset.eq(counter.reset),
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scrambler.ce.eq(counter.ce)
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]
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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self.done.eq(1),
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counter.reset.eq(1),
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If(self.start,
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self.ctrl_error_counter.reset.eq(1),
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self.data_error_counter.reset.eq(1),
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If(self.read_only,
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NextState("SEND_READ_CMD")
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).Else(
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NextState("SEND_WRITE_CMD_AND_DATA")
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)
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)
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)
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fsm.act("SEND_WRITE_CMD_AND_DATA",
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source.stb.eq(1),
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source.sop.eq((counter.value == 0)),
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source.eop.eq((counter.value == (sata_con.sector_size//4*self.count)-1)),
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source.write.eq(1),
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source.sector.eq(self.sector),
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source.count.eq(self.count),
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source.data.eq(scrambler.value),
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counter.ce.eq(source.ack),
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If(source.stb & source.eop & source.ack,
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NextState("WAIT_WRITE_ACK")
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)
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)
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fsm.act("WAIT_WRITE_ACK",
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sink.ack.eq(1),
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If(sink.stb,
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If(~sink.write | ~sink.success | sink.failed,
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self.ctrl_error_counter.ce.eq(1)
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),
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If(self.write_only,
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NextState("IDLE")
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).Else(
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NextState("SEND_READ_CMD")
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)
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)
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)
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fsm.act("SEND_READ_CMD",
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source.stb.eq(1),
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source.sop.eq(1),
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source.eop.eq(1),
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source.read.eq(1),
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source.sector.eq(self.sector),
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source.count.eq(self.count),
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If(source.ack,
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NextState("WAIT_READ_ACK")
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)
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)
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fsm.act("WAIT_READ_ACK",
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counter.reset.eq(1),
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If(sink.stb & sink.read,
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If(~sink.read | ~sink.success | sink.failed,
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self.ctrl_error_counter.ce.eq(1)
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),
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NextState("RECEIVE_READ_DATA")
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)
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)
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fsm.act("RECEIVE_READ_DATA",
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sink.ack.eq(1),
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If(sink.stb,
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counter.ce.eq(1),
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If(sink.data != scrambler.value,
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self.data_error_counter.ce.eq(1)
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),
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If(sink.eop,
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NextState("IDLE")
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)
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)
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)
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class SATABIST(Module, AutoCSR):
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def __init__(self, sata_con):
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self._start = CSR()
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self._start_sector = CSRStorage(48)
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self._count = CSRStorage(4)
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self._write_only = CSRStorage()
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self._read_only = CSRStorage()
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self._stop = CSRStorage()
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self._sector = CSRStatus(48)
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self._errors = CSRStatus(32)
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start = self._start.r & self._start.re
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start_sector = self._start_sector.storage
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count = self._count.storage
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stop = self._stop.storage
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compute = Signal()
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write_only = self._write_only.storage
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read_only = self._read_only.storage
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sector = self._sector.status
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errors = self._errors.status
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###
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self.unit = SATABISTUnit(sata_con)
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self.comb += [
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self.unit.write_only.eq(write_only),
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self.unit.read_only.eq(read_only),
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self.unit.sector.eq(sector),
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self.unit.count.eq(count)
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]
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self.fsm = fsm = FSM(reset_state="IDLE")
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# FSM
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fsm.act("IDLE",
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If(start,
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NextState("START")
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)
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)
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fsm.act("START",
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self.unit.start.eq(1),
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NextState("WAIT_DONE")
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)
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fsm.act("WAIT_DONE",
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If(self.unit.done,
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NextState("COMPUTE")
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).Elif(stop,
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NextState("IDLE")
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)
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)
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fsm.act("COMPUTE",
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compute.eq(1),
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NextState("START")
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)
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self.sync += [
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If(start,
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errors.eq(0),
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sector.eq(start_sector)
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).Elif(compute,
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errors.eq(errors + self.unit.data_errors),
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sector.eq(sector + count)
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)
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]
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