Jędrzej Boczar 76d121ea36 soc/software/liblitedram: add DQ-DQS training procedure		2021-04-16 11:50:38 +02:00
..
build	Merge pull request #874 from chmousset/enh/ECP5DifferentialInput	2021-04-06 12:27:33 +02:00
compat	compat/stream_sim: Remove TODO since will not be done.	2021-03-24 17:58:13 +01:00
gen	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
soc	soc/software/liblitedram: add DQ-DQS training procedure	2021-04-16 11:50:38 +02:00
tools	tools/litex_client: Add filter parameter to dump_registrers to only dump/display the filtered registers:	2021-04-13 13:44:41 +02:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00