Florent Kermarrec 7a4ecfa59d targets/kcu105: update		2020-01-15 13:17:59 +01:00
..
boards	targets/kcu105: update	2020-01-15 13:17:59 +01:00
build	Add optional 'ignore-loops' flag to nextpnr	2020-01-10 16:07:56 +01:00
gen	gen/fhdl/verilog: fix signed init values	2020-01-12 22:06:35 +01:00
soc	SoCCore: set default integrated_rom/ram_size to 0. For targets, defaults values are provided by soc_core_args.	2020-01-15 10:59:01 +01:00
tools	tools/litex_sim: use default integrated_rom_size	2020-01-13 17:39:23 +01:00
__init__.py	soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)	2019-09-30 23:41:07 +02:00