Werner Almesberger 7a6e56492c edid.py: sample SCL only every 64 clock cycles, to avoid bouncing ... Possibly due to SCL rising fairly slowly (in the 0.5-1 us range), bouncing has been observed while crossing the "forbidden" region between Vil(max) and Vih(min). By lowering the sample rate from once per system clock to once every 64 clock cycles, we make sure we sample at most once during the bounce interval and thus never see a false edge. (Although we may see a rising edge one sample time late, which is perfectly harmless.)		2013-04-12 22:48:46 +02:00
..
asmicon	Use new module, autoreg and eventmanager Migen APIs	2013-03-10 19:32:38 +01:00
asmiprobe	Convert to new CSR API	2013-03-30 17:28:15 +01:00
dfii	dfii: adapt to new Record API	2013-04-02 00:15:42 +02:00
dvisampler	edid.py: sample SCL only every 64 clock cycles, to avoid bouncing	2013-04-12 22:48:46 +02:00
framebuffer	framebuffer: use new flow API	2013-04-10 21:34:15 +02:00
identifier	Convert to new CSR API	2013-03-30 17:28:15 +01:00
lm32	Use Instance.Input(..., ClockSignal/ResetSignal) instead of Instance.ClockPort/ResetPort	2013-03-18 17:44:01 +01:00
m1crg	Convert to new CSR API	2013-03-30 17:28:15 +01:00
minimac3	Convert to new CSR API	2013-03-30 17:28:15 +01:00
norflash	Use new Mibuild generic_platform API	2013-03-26 17:57:17 +01:00
s6ddrphy	Use new Mibuild generic_platform API	2013-03-26 17:57:17 +01:00
timer	Convert to new CSR API	2013-03-30 17:28:15 +01:00
uart	Convert to new CSR API	2013-03-30 17:28:15 +01:00
__init__.py	Initial import	2011-12-13 17:33:12 +01:00