144 lines
4.4 KiB
Python
144 lines
4.4 KiB
Python
from mibuild.generic_platform import *
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from mibuild.crg import SimpleCRG
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from mibuild.xilinx.ise import XilinxISEPlatform
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from mibuild.xilinx.programmer import XC3SProg
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_io = [
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("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at hdmi
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("user_led", 1, Pins("U16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at hdmi
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("user_led", 2, Pins("A16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at msd
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("user_led", 3, Pins("A15"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at msd
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("user_led", 4, Pins("A12"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at usb
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("user_switch", 0, Pins("N14"), IOStandard("LVTTL"), Misc("PULLDOWN")),
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("clk50", 0, Pins("H17"), IOStandard("LVTTL")),
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("serial", 0,
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Subsignal("tx", Pins("A10")),
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Subsignal("rx", Pins("A11"), Misc("PULLUP")),
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Subsignal("rts", Pins("C10")),
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Subsignal("cts", Pins("A9"), Misc("PULLUP")),
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IOStandard("LVTTL"),
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),
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("usb_fifo", 0,
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Subsignal("data", Pins("A11 A10 C10 A9 B9 A8 B8 A7")),
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Subsignal("rxf", Pins("C7")),
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Subsignal("txe", Pins("A6")),
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Subsignal("rd", Pins("B6")),
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Subsignal("wr", Pins("A5")),
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Subsignal("siwua", Pins("C5")),
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IOStandard("LVTTL"),
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),
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("hdmi", 0,
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Subsignal("clk_p", Pins("U5"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("V5"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("T6"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("V6"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("U7"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("V7"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("U8"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("V8"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("V9"), IOStandard("I2C")),
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Subsignal("sda", Pins("T9"), IOStandard("I2C")),
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Subsignal("hpd_notif", Pins("R8"), IOStandard("LVTTL")),
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),
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("spiflash", 0,
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Subsignal("cs_n", Pins("V3")),
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Subsignal("clk", Pins("R15")),
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Subsignal("mosi", Pins("T13")),
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Subsignal("miso", Pins("R13"), Misc("PULLUP")),
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Subsignal("wp", Pins("T14")),
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Subsignal("hold", Pins("V14")),
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IOStandard("LVTTL"), Misc("SLEW=FAST")
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),
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("spiflash2x", 0,
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Subsignal("cs_n", Pins("V3")),
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Subsignal("clk", Pins("R15")),
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Subsignal("dq", Pins("T13 R13"), Misc("PULLUP")),
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Subsignal("wp", Pins("T14")),
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Subsignal("hold", Pins("V14")),
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IOStandard("LVTTL"), Misc("SLEW=FAST")
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("V3")),
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Subsignal("clk", Pins("R15")),
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Subsignal("dq", Pins("T13 R13 T14 V14"), Misc("PULLUP")),
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IOStandard("LVTTL"), Misc("SLEW=FAST")
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),
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("mmc", 0,
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Subsignal("clk", Pins("A3")),
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Subsignal("cmd", Pins("B3"), Misc("PULLUP")),
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Subsignal("dat", Pins("B4 A4 B2 A2"), Misc("PULLUP")),
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IOStandard("SDIO")
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),
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("mmc_spi", 0,
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Subsignal("cs_n", Pins("A2"), Misc("PULLUP")),
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Subsignal("clk", Pins("A3")),
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Subsignal("mosi", Pins("B3")),
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Subsignal("miso", Pins("B4"), Misc("PULLUP")),
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IOStandard("SDIO")
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),
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("audio", 0,
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Subsignal("l", Pins("R7"), Misc("SLEW=SLOW")),
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Subsignal("r", Pins("T7"), Misc("SLEW=SLOW")),
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IOStandard("LVTTL"),
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),
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("pmod", 0,
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Subsignal("d", Pins("D9 C8 D6 C4 B11 C9 D8 C6")),
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IOStandard("LVTTL")
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),
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("sdram_clock", 0,
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Subsignal("p", Pins("G3")),
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Subsignal("n", Pins("G1")),
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IOStandard("MOBILE_DDR")
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),
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("sdram", 0,
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Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")),
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Subsignal("ba", Pins("F2 F1")),
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Subsignal("cke", Pins("H7")),
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Subsignal("ras_n", Pins("L5")),
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Subsignal("cas_n", Pins("K5")),
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Subsignal("we_n", Pins("E3")),
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Subsignal("dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 M3 M1 N2 N1 T2 T1 U2 U1")),
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Subsignal("dqs", Pins("L4 P2")),
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Subsignal("dm", Pins("K3 K4")),
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IOStandard("MOBILE_DDR")
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)
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]
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_connectors = [
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("A", "U18 T17 P17 P16 N16 N17 M16 L15 L17 K15 K17 J16 H15 H18 F18 D18"),
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("B", "C18 E18 G18 H16 J18 K18 K16 L18 L16 M18 N18 N15 P15 P18 T18 U17"),
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("C", "F17 F16 E16 G16 F15 G14 F14 H14 H13 J13 G13 H12 K14 K13 K12 L12"),
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]
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class Platform(XilinxISEPlatform):
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identifier = 0x5049
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default_clk_name = "clk50"
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default_clk_period = 20
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def __init__(self):
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XilinxISEPlatform.__init__(self, "xc6slx45-csg324-2", _io,
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lambda p: SimpleCRG(p, "clk50", None), _connectors)
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def create_programmer(self):
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return XC3SProg("papilio", "bscan_spi_lx45_csg324.bit")
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def do_finalize(self, fragment):
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try:
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self.add_period_constraint(self.lookup_request("clk50"), 20.)
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except ConstraintError:
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pass
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