Leon Schuermann 7b533a032d litex_sim: rewrite XGMII verilator module and add support in litex_sim ... Signed-off-by: Leon Schuermann <leon@is.currently.online>		2021-09-01 20:44:45 +02:00
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build	litex_sim: rewrite XGMII verilator module and add support in litex_sim	2021-09-01 20:44:45 +02:00
compat	soc/add_spi_flash: Move integration code for previous LiteX SPI Flash core to compat/soc_add_spi_flash.py.	2021-07-29 18:48:03 +02:00
gen	gen/fhdl/verilog: Make DummyAttrTranslate a dict.	2021-07-15 16:48:24 +02:00
soc	soc/add_cpu: Add memory mapping overrides to build log and make an exception for the CPUNone case.	2021-07-30 15:00:10 +02:00
tools	litex_sim: rewrite XGMII verilator module and add support in litex_sim	2021-09-01 20:44:45 +02:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00