Florent Kermarrec 7dbd85a842 soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx)		2018-07-10 22:32:51 +02:00
..
cores	soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx)	2018-07-10 22:32:51 +02:00
integration	soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another)	2018-07-10 13:29:32 +02:00
interconnect	soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another)	2018-07-10 13:29:32 +02:00
software	bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup)	2018-07-06 19:22:33 +02:00
tools	setup: add vexriscv_debug to list of entrypoints	2018-07-06 16:22:11 +08:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
MISOC_LICENSE	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00