litex/misoclib/com/liteusb
Florent Kermarrec dc8d844579 liteusb: begin refactoring and simplification (wip) 2015-04-27 15:22:49 +02:00
..
core liteusb: begin refactoring and simplification (wip) 2015-04-27 15:22:49 +02:00
frontend liteusb: begin refactoring and simplification (wip) 2015-04-27 15:22:49 +02:00
generic merge liteusb 2015-02-28 11:16:16 +01:00
phy liteusb: begin refactoring and simplification (wip) 2015-04-27 15:22:49 +02:00
software/ftdi/ft2232h liteusb: begin refactoring and simplification (wip) 2015-04-27 15:22:49 +02:00
test liteusb: begin refactoring and simplification (wip) 2015-04-27 15:22:49 +02:00
LICENSE liteusb: move files and modify import to misoclib.com.liteusb 2015-02-28 11:18:00 +01:00
README liteXXX cores: update README and doc 2015-02-28 21:40:59 +01:00
__init__.py liteusb: begin refactoring and simplification (wip) 2015-04-27 15:22:49 +02:00
common.py liteusb: begin refactoring and simplification (wip) 2015-04-27 15:22:49 +02:00

README

            __   _ __      __  _________
           / /  (_) /____ / / / / __/ _ )
          / /__/ / __/ -_) /_/ /\ \/ _  |
         /____/_/\__/\__/\____/___/____/

          Copyright 2015 / EnjoyDigital / M-Labs Ltd

   	  A small footprint and configurable USB core
                powered by Migen

[> Doc
---------
XXX

[> Intro
---------
LiteUSB provides a small footprint and configurable USB core.

LiteUSB is part of MiSoC libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations
ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...

The core uses simple and specific streaming buses and will provides in the future
adapters to use standardized AXI or Avalon-ST streaming buses.

Since Python is used to describe the HDL, the core is highly and easily
configurable.

LiteUSB uses technologies developed in partnership with M-Labs Ltd:
 - Migen enables generating HDL with Python in an efficient way.
 - MiSoC provides the basic blocks to build a powerful and small footprint SoC.

LiteUSB can be used as MiSoC library or can be integrated with your standard
design flow by generating the verilog rtl that you will use as a standard core.

[> Features
-----------
- FTDI2232 slave fifo core (DMA, virtual TTY) + host software

[> Possible improvements
-------------------------
- add Cypress FX2 support
- add Cypress FX3 support
- add USB3 transceiver support and use Daisho's USB3 stack?
- ... See below Support and consulting :)

If you want to support these features, please contact us at florent [AT]
enjoy-digital.fr. You can also contact our partner on the public mailing list
devel [AT] lists.m-labs.hk.


[> Getting started
------------------
XXX

[> Simulations:
XXX

[> Tests :
XXX

[> License
-----------
LiteUSB is released under the very permissive two-clause BSD license. Under
the terms of this license, you are authorized to use LiteUSB for closed-source
proprietary designs.
Even though we do not require you to do so, those things are awesome, so please
do them if possible:
 - tell us that you are using LiteUSB
 - cite LiteUSB in publications related to research it has helped
 - send us feedback and suggestions for improvements
 - send us bug reports when something goes wrong
 - send us the modifications and improvements you have done to LiteUSB.

[> Support and consulting
--------------------------
We love open-source hardware and like sharing our designs with others.

LiteUSB is mainly developed and maintained by EnjoyDigital.

If you would like to know more about LiteUSB or if you are already a happy
user and would like to extend it for your needs, EnjoyDigital can provide standard
commercial support as well as consulting services.

So feel free to contact us, we'd love to work with you! (and eventually shorten
the list of the possible improvements :)

[> Contact
E-mail: florent [AT] enjoy-digital.fr