enjoy-digital 836d5b88c5 Merge pull request #266 from xobs/add-moduledoc-autodoc ... Add ModuleDoc and AutoDoc		2019-09-24 10:09:22 +02:00
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boards	boards/targets: increase integrated ROM size if EthernetSoC is used	2019-09-23 15:34:34 +02:00
build	vivado just needs to be in the path for the programmer as well	2019-09-19 20:35:55 -07:00
gen	gen/fhdl/verilog: allow single element verilog inline attribute	2019-08-28 05:24:11 +02:00
soc	Merge pull request #266 from xobs/add-moduledoc-autodoc	2019-09-24 10:09:22 +02:00
tools	tools/litex_read_verilog: also delete yosys_v2j.ys	2019-09-24 08:49:00 +02:00
__init__.py	tools: move from litex.soc.tools to litex.tools and fix usb.core import	2019-04-20 10:44:53 +02:00