87d456cae2
For the "P" side of the analog channels, actually, connecting a digital line to them has "no meaning". The docs say that either you connect an analog pin to a pad, or vivado "ties it off appropriately". I wish it were the case that tying a pin to 0 or 1 would actually connect it to a power or ground, because it means that even in unipolar mode you have to burn two pins to break out the signal of interest *and* the ground reference analog pad (I thought I could just connect it to "0" and the pin would be grounded, but that doesn't happen -- it's just ignored if it's not wired to a pad). For the pad specifier, is it OK to leave it with an optional argument of analog_pads=None? I tried assigning to the self.analog property after instantiation, but this doesn't seem to work, the default values are preferred. It looks like if you don't want to do the analog_pads= optional argument the other way to do it would be to add code on the instiating module that tampers with the properties of the instance directly, but I think that's sort of ugly. Also, I noticed you stripped out the layout specifier for the analog_pads. I thought it would be nice to provide that in the file, so the caller doesn't have to infer what the pad layout is by reading the code...what's the motivation for removing that? |
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| doc | ||
| litex | ||
| test | ||
| .gitignore | ||
| .gitmodules | ||
| .travis.yml | ||
| CONTRIBUTORS | ||
| LICENSE | ||
| MANIFEST.in | ||
| README.md | ||
| litex_setup.py | ||
| setup.py | ||
README.md
Copyright 2012-2019 / EnjoyDigital
Welcome to LiteX!
LiteX is a FPGA design/SoC builder that can be used to build cores, create SoCs and full FPGA designs.
LiteX is based on Migen and provides specific building/debugging tools for a higher level of abstraction and compatibily with the LiteX core ecosystem.
Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a SoC builder to create/develop/debug FPGA SoCs in Python.
Typical LiteX design flow:
+---------------+
|FPGA toolchains|
+----^-----+----+
| |
+--+-----v--+
+-------+ | |
| Migen +--------> |
+-------+ | | Your design
| LiteX +---> ready to be used!
| |
+----------------------+ | |
|LiteX Cores Ecosystem +--> |
+----------------------+ +-^-------^-+
(Eth, SATA, DRAM, USB, | |
PCIe, Video, etc...) + +
board target
file file
LiteX already supports various softcores CPUs: LM32, Mor1kx, PicoRV32, VexRiscv and is compatible with the LiteX's Cores Ecosystem:
| Name | Build Status | Description |
|---|---|---|
| LiteDRAM |  |
DRAM |
| LiteEth |  |
Ethernet |
| LitePCIe |  |
PCIe |
| LiteSATA |  |
SATA |
| LiteSDCard |  |
SD card |
| LiteICLink |  |
Inter-Chip communication |
| LiteJESD204B |  |
JESD204B |
| LiteVideo |  |
VGA, DVI, HDMI |
| LiteScope |  |
Logic analyzer |
Sub-packages
litex.gen Provides specific or experimental modules to generate HDL that are not integrated in Migen.
litex.build: Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to simulate HDL code or full SoCs.
litex.soc: Provides definitions/modules to build cores (bus, bank, flow), cores and tools to build a SoC from such cores.
litex.boards: Provides platforms and targets for the supported boards. All Migen's platforms can also be used in LiteX. The boards present in the LiteX repository are the official ones that are used for development/CI. More boards are available at: https://github.com/litex-hub/litex-boards
Papers, Presentations, Tutorials, Links
FPGA lessons/tutorials:
OSDA paper/slides:
Linux on LiteX-Vexriscv:
RISC-V Getting Started Guide:
LiteX vs. Vivado First Impressions:
35C3 - Snakes and Rabbits - How CCC shaped an open hardware success:
Tim has to many projects - LatchUp Edition: https://www.youtube.com/watch?v=v7WrTmexod0
Very Quick start guide (for newcomers)
TimVideos.us has done an awesome job for setting up a LiteX environment easily in the litex-buildenv repo: https://github.com/timvideos/litex-buildenv
It's recommended for newcomers to go this way. Various FPGA boards are supported and multiple examples provided! You can even run Linux on your FPGA using LiteX very easily!
Migen documentation can be found here: https://m-labs.hk/migen/manual
Quick start guide (for advanced users)
- Install Python 3.5+ and FPGA vendor's development tools.
- Install Migen/LiteX and the LiteX's cores:
$ wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
$ chmod +x litex_setup.py
$ ./litex_setup.py init install --user (--user to install to user directory)
Later, if you need to update all repositories:
$ ./litex_setup.py update
- Install a RISC-V toolchain:
$ wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
$ tar -xvf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
$ export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/
-
Build the target of your board...: Go to litex-boards/litex_boards/xxyy/targets (xxyy being community/official/partner) and execute the target you want to build
-
... and/or install Verilator and test LiteX on your computer: Download and install Verilator: http://www.veripool.org/ On Fedora:
$ sudo dnf install libevent-devel json-c-devel
On Ubuntu:
$ sudo apt install libevent-dev libjson-c-dev
$ litex_sim
- Run a terminal program on the board's serial port at 115200 8-N-1. You should get the BIOS prompt.
Contact
E-mail: florent@enjoy-digital.fr