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88e7fa21e4
litex
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misoclib
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mem
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litesata
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example_designs
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Florent Kermarrec
649cdeb265
liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
2015-03-01 16:48:41 +01:00
..
platforms
litesata: create specialized kc705 platform to avoid duplicating things already in mibuild
2015-03-01 11:03:15 +01:00
targets
liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
2015-03-01 16:48:41 +01:00
test
liteXXX cores: share same methodology for on-board tests
2015-03-01 11:21:12 +01:00
make.py
litesata: create example design derived from SoC
2015-03-01 11:33:38 +01:00