litex/litex
2016-04-19 16:02:26 +10:00
..
boards soc/cores/sdram/settings: simplify modules and fix timing margins computation 2016-04-18 18:22:53 +02:00
build build/xilinx/ise: use Tim's fix on add_period_constraint and add_false_path_constraint 2016-04-14 21:48:52 +02:00
gen
soc bios: Print CPU architecture on boot. 2016-04-19 16:02:26 +10:00
__init__.py