Sebastien Bourdeauducq 8a61d9d121 bus/csr: Rename a->adr d->dat to be consistent with the other buses		2012-02-13 21:46:39 +01:00
..
actorlib	Use enumerate(x) instead of zip(range(x), x)	2012-02-02 21:28:00 +01:00
bank	bus/csr: Rename a->adr d->dat to be consistent with the other buses	2012-02-13 21:46:39 +01:00
bus	bus/csr: Rename a->adr d->dat to be consistent with the other buses	2012-02-13 21:46:39 +01:00
corelogic	corelogic/misc: displacer + chooser	2012-02-11 20:57:08 +01:00
fhdl	fhdl: do not attempt slicing non-array signals to keep Verilog happy	2012-02-06 18:07:02 +01:00
flow	Use enumerate(x) instead of zip(range(x), x)	2012-02-02 21:28:00 +01:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00