litex/migen/bus
Sebastien Bourdeauducq 8a61d9d121 bus/csr: Rename a->adr d->dat to be consistent with the other buses 2012-02-13 21:46:39 +01:00
..
__init__.py CSR bus definitions 2011-12-05 00:16:44 +01:00
asmibus.py bus/asmibus: fix typo 2012-02-11 20:56:01 +01:00
csr.py bus/csr: Rename a->adr d->dat to be consistent with the other buses 2012-02-13 21:46:39 +01:00
simple.py Remove explicit bus names and rely on the new automatic namer 2012-01-27 22:20:57 +01:00
wishbone.py Remove explicit bus names and rely on the new automatic namer 2012-01-27 22:20:57 +01:00
wishbone2asmi.py bus/wishbone2asmi: set WM, and send 0 when inactive 2012-02-13 16:49:43 +01:00
wishbone2csr.py bus/csr: Rename a->adr d->dat to be consistent with the other buses 2012-02-13 21:46:39 +01:00