Florent Kermarrec 8c50366d15 litespi/spiflash: Use shorted message when first SPI Flash block is erased and freq test cannot be done.		2021-09-02 11:26:56 +02:00
..
build	build: add DDRTristate	2021-08-27 13:51:58 +02:00
compat	soc/add_spi_flash: Move integration code for previous LiteX SPI Flash core to compat/soc_add_spi_flash.py.	2021-07-29 18:48:03 +02:00
gen	gen/fhdl/verilog: Make DummyAttrTranslate a dict.	2021-07-15 16:48:24 +02:00
soc	litespi/spiflash: Use shorted message when first SPI Flash block is erased and freq test cannot be done.	2021-09-02 11:26:56 +02:00
tools	tools/litex_contributors: Add special cases for companies to replace individuals with company name/email.	2021-09-01 11:09:26 +02:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00