litex/litex
Florent Kermarrec 8d999081e3 boards/targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support. 2020-03-24 20:04:18 +01:00
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boards boards/targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support. 2020-03-24 20:04:18 +01:00
build build/lattice/diamond: remove ECP3 support. (ECP3 is not used and no longer interesting now that ECP5 has an open-source toolchain). 2020-03-24 19:36:57 +01:00
gen gen/fhdl/verilog: fix signed init values 2020-01-12 22:06:35 +01:00
soc cores/clock/ECP5PLL: add phase support. 2020-03-24 19:09:05 +01:00
tools litex_sim: add support for hybrid mac 2020-03-19 10:04:08 +01:00
__init__.py soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) 2019-09-30 23:41:07 +02:00