Rafal Kolucki 8ef51a00ee soc/interconnect/wishbone: Add incrementing burst cycles support to SRAM ... This commit adds support for incrementing burst cycles in SRAM peripheral. By default it's enabled, but can be disabled by passing `burst=False` to the class while initializing, if it won't be useful for created design (e.g. no Wishbone bus masters with burst support).		2022-04-12 14:06:22 +02:00
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build	soc/build: Remove Migen Git SHA1 from auto-generated headers/bios (Hasn't been useful).	2022-04-11 09:50:00 +02:00
compat	cores/spi_flash: Deprecate SPI Flash MMAPed cores (Designs have been switched with LiteSPI).	2022-01-07 19:08:03 +01:00
gen	soc/cores/jtag: Review/Cleanup JTAGTAPFSM and avoid specific CorrectedOngoingResetFSM.	2022-01-31 16:07:50 +01:00
soc	soc/interconnect/wishbone: Add incrementing burst cycles support to SRAM	2022-04-12 14:06:22 +02:00
tools	tools/litex_sim: Use new get_boot_address function.	2022-03-17 17:46:27 +01:00
__init__.py	…