litex/migen
Sebastien Bourdeauducq 8f69d9b669 bank/eventmanager: add SharedIRQ 2014-01-06 22:13:06 +01:00
..
actorlib actorlib/spi/DMAWriteController: make ack_when_inactive a keyword-only arg 2013-11-02 23:21:05 +01:00
bank bank/eventmanager: add SharedIRQ 2014-01-06 22:13:06 +01:00
bus bus/wishbone/sram: expose memory component 2013-11-24 23:43:14 +01:00
fhdl migen/fhdl/tools: speed up group_by_targets (halves the mixxeo runtime) 2013-12-17 18:40:49 +01:00
flow flow/isd: update to new APIs 2013-11-20 17:45:09 +01:00
genlib fhdl.size: rename to bitcontainer 2013-12-03 22:51:52 +01:00
pytholite replace use of __dict__ with dir()/xdir() 2013-11-02 16:03:47 +01:00
sim sim: use Simulator as a contextmanager 2013-11-29 23:05:15 +01:00
test migen/test/test_signed: add a (currently failing) signed comparison testcase 2013-12-10 23:33:53 +01:00
util utils/misc: add gcd_multiple function to compute GCD or any number of integers 2013-12-12 17:36:50 +01:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00