36 lines
1009 B
Python
36 lines
1009 B
Python
import unittest
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from migen.fhdl.std import *
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from migen.genlib.fifo import SyncFIFO, AsyncFIFO
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from migen.test.support import SimCase, SimBench
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class SyncFIFOCase(SimCase, unittest.TestCase):
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class TestBench(SimBench):
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def __init__(self):
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self.submodules.dut = SyncFIFO([("a", 32), ("b", 32)], 2)
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self.sync += [
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If(self.dut.we & self.dut.writable,
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self.dut.din.a.eq(self.dut.din.a + 1),
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self.dut.din.b.eq(self.dut.din.b + 2)
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)
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]
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def test_sizes(self):
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self.assertEqual(flen(self.tb.dut.din_bits), 64)
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self.assertEqual(flen(self.tb.dut.dout_bits), 64)
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def test_run_sequence(self):
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seq = list(range(20))
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def cb(tb, s):
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# fire re and we at "random"
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s.wr(tb.dut.we, s.cycle_counter % 2 == 0)
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s.wr(tb.dut.re, s.cycle_counter % 3 == 0)
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# the output if valid must be correct
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if s.rd(tb.dut.readable) and s.rd(tb.dut.re):
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i = seq.pop(0)
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self.assertEqual(s.rd(tb.dut.dout.a), i)
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self.assertEqual(s.rd(tb.dut.dout.b), i*2)
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self.run_with(cb, 20)
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