Florent Kermarrec 90c485fcc8 integration/soc: add clock_domain parameter to add_etherbone. ... To allow using a sys_clk < 125MHz with a 1Gbps link.		2020-05-08 13:16:26 +02:00
..
cores	integration/soc: add add_uartbone method (to add a UARTBone aka UART Wishbone bridge).	2020-05-08 11:54:51 +02:00
doc	soc/doc/csr: allow CSRField.reset to be a Migen Constant.	2020-03-23 18:47:41 +01:00
integration	integration/soc: add clock_domain parameter to add_etherbone.	2020-05-08 13:16:26 +02:00
interconnect	Small fixups to address compiler warnings etc.	2020-05-07 09:26:46 +01:00
software	bios/sdram: fix lfsr typo.	2020-05-07 12:11:59 +02:00
__init__.py