Florent Kermarrec 90c485fcc8 integration/soc: add clock_domain parameter to add_etherbone. ... To allow using a sys_clk < 125MHz with a 1Gbps link.		2020-05-08 13:16:26 +02:00
..
boards	boards/platforms: update xilinx programmers.	2020-05-06 16:16:41 +02:00
build	build/xilinx: add disable_constraints parameter to Platform.add_ip.	2020-05-07 11:34:26 +02:00
gen	gen/fhdl/verilog: explicitly define input/output/inout wires.	2020-05-05 16:58:33 +02:00
soc	integration/soc: add clock_domain parameter to add_etherbone.	2020-05-08 13:16:26 +02:00
tools	Update README.md	2020-05-02 02:51:41 -04:00
__init__.py	litex/__init__.py: remove retro-compat > 6 months old.	2020-04-30 21:31:58 +02:00