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cpu
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cores/cpu: add software informations to cpu and simplify cpu_interface
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2018-09-24 07:51:41 +02:00 |
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__init__.py
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litex: reorganize things, first work working version
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2015-11-07 17:48:55 +01:00 |
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clock.py
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soc/cores/clock: different vco_freq_range for pll and mmcm
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2018-09-25 09:04:38 +02:00 |
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code_8b10b.py
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soc/cores/code_8b10b: update (from misoc)
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2018-06-29 14:24:44 +02:00 |
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cordic.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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dna.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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frequency_meter.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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gpio.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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identifier.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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nor_flash_16.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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spi.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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spi_flash.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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timer.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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uart.py
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soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx)
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2018-07-10 22:32:51 +02:00 |
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xadc.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
