litex/litex
2019-05-14 11:45:12 +02:00
..
boards boards/targets/de0nano: reduce to 50MHz sys_clk, simplify CRG 2019-05-14 11:45:12 +02:00
build build/sim: update tapcfg 2019-05-01 12:34:12 +02:00
gen soc/integration: also add sha-1/date to generated software files 2019-04-23 13:17:54 +02:00
soc cpu/vexriscv/core: update 2019-05-13 10:59:26 +02:00
tools boards/targets: use new add_csr method 2019-05-09 23:50:43 +02:00
__init__.py tools: move from litex.soc.tools to litex.tools and fix usb.core import 2019-04-20 10:44:53 +02:00