Florent Kermarrec 144ee7ea9f soc: fix register_rom		2015-02-28 23:51:51 +01:00
..
__init__.py	soc: fix register_rom	2015-02-28 23:51:51 +01:00
cpuif.py	remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)	2015-02-28 11:36:15 +01:00
sdram.py	test implementation on all targets and fix issues	2015-02-28 12:04:51 +01:00