|
__init__.py
|
CSR bus definitions
|
2011-12-05 00:16:44 +01:00 |
|
asmibus.py
|
bus/asmicon: initiator
|
2012-03-30 22:16:31 +02:00 |
|
csr.py
|
bus: simplify and cleanup
|
2012-02-15 16:30:16 +01:00 |
|
dfi.py
|
bus/dfi: fix multiphase naming
|
2012-02-19 17:57:04 +01:00 |
|
simple.py
|
bus: add interconnect statements function
|
2012-02-17 23:51:32 +01:00 |
|
transactions.py
|
bus: generic transaction model
|
2012-03-08 18:14:06 +01:00 |
|
wishbone.py
|
bus: generic transaction model
|
2012-03-08 18:14:06 +01:00 |
|
wishbone2asmi.py
|
fhdl: export log2_int
|
2012-03-14 12:19:42 +01:00 |
