226 lines
7.9 KiB
Python
226 lines
7.9 KiB
Python
from migen.fhdl.std import log2_int
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def get_sdram_phy_header(sdram_phy_settings):
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r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
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r += "#include <hw/common.h>\n#include <generated/csr.h>\n#include <hw/flags.h>\n\n"
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nphases = sdram_phy_settings.nphases
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r += "#define DFII_NPHASES "+str(nphases)+"\n\n"
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r += "static void cdelay(int i);\n"
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# commands_px functions
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for n in range(nphases):
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r += """
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static void command_p{n}(int cmd)
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{{
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sdram_dfii_pi{n}_command_write(cmd);
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sdram_dfii_pi{n}_command_issue_write(1);
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}}""".format(n=str(n))
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r += "\n\n"
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# rd/wr access macros
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r += """
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#define sdram_dfii_pird_address_write(X) sdram_dfii_pi{rdphase}_address_write(X)
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#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi{wrphase}_address_write(X)
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#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi{rdphase}_baddress_write(X)
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#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi{wrphase}_baddress_write(X)
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#define command_prd(X) command_p{rdphase}(X)
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#define command_pwr(X) command_p{wrphase}(X)
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""".format(rdphase=str(sdram_phy_settings.rdphase), wrphase=str(sdram_phy_settings.wrphase))
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r +="\n"
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#
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# sdrrd/sdrwr functions utilities
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#
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r += "#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE\n"
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sdram_dfii_pix_wrdata_addr = []
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for n in range(nphases):
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sdram_dfii_pix_wrdata_addr.append("CSR_SDRAM_DFII_PI{n}_WRDATA_ADDR".format(n=n))
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r += """
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const unsigned int sdram_dfii_pix_wrdata_addr[{n}] = {{
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{sdram_dfii_pix_wrdata_addr}
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}};
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""".format(n=nphases, sdram_dfii_pix_wrdata_addr=",\n\t".join(sdram_dfii_pix_wrdata_addr))
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sdram_dfii_pix_rddata_addr = []
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for n in range(nphases):
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sdram_dfii_pix_rddata_addr.append("CSR_SDRAM_DFII_PI{n}_RDDATA_ADDR".format(n=n))
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r += """
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const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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{sdram_dfii_pix_rddata_addr}
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}};
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""".format(n=nphases, sdram_dfii_pix_rddata_addr=",\n\t".join(sdram_dfii_pix_rddata_addr))
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r +="\n"
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# init sequence
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cmds = {
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"PRECHARGE_ALL" : "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"MODE_REGISTER" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"AUTO_REFRESH" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
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"UNRESET" : "DFII_CONTROL_ODT|DFII_CONTROL_RESET_N",
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"CKE" : "DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N"
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}
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cl = sdram_phy_settings.cl
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if sdram_phy_settings.memtype == "SDR":
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bl = sdram_phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 20000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif sdram_phy_settings.memtype == "DDR":
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bl = 2*sdram_phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 20000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif sdram_phy_settings.memtype == "LPDDR":
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bl = 2*sdram_phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 20000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 2, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif sdram_phy_settings.memtype == "DDR2":
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bl = 2*sdram_phy_settings.nphases
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wr = 2
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mr = log2_int(bl) + (cl << 4) + (wr << 9)
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emr = 0
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emr2 = 0
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emr3 = 0
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reset_dll = 1 << 8
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ocd = 7 << 7
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 20000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register 3", emr3, 3, cmds["MODE_REGISTER"], 0),
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("Load Extended Mode Register 2", emr2, 2, cmds["MODE_REGISTER"], 0),
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("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200),
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("Load Extended Mode Register / OCD Default", emr+ocd, 1, cmds["MODE_REGISTER"], 0),
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("Load Extended Mode Register / OCD Exit", emr, 1, cmds["MODE_REGISTER"], 0),
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]
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elif sdram_phy_settings.memtype == "DDR3":
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bl = 2*sdram_phy_settings.nphases
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if bl != 8:
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raise NotImplementedError("DDR3 PHY header generator only supports BL of 8")
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def format_mr0(cl, wr, dll_reset):
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cl_to_mr0 = {
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5 : 0b0010,
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6 : 0b0100,
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7 : 0b0110,
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8 : 0b1000,
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9 : 0b1010,
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10: 0b1100,
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11: 0b1110,
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12: 0b0001,
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13: 0b0011,
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14: 0b0101
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}
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wr_to_mr0 = {
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16: 0b000,
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5 : 0b001,
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6 : 0b010,
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7 : 0b011,
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8 : 0b100,
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10: 0b101,
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12: 0b110,
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14: 0b111
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}
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mr0 = (cl_to_mr0[cl] & 1) << 2
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mr0 |= ((cl_to_mr0[cl] >> 1) & 0b111) << 4
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mr0 |= dll_reset << 8
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mr0 |= wr_to_mr0[wr] << 9
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return mr0
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def format_mr1(output_drive_strength, rtt_nom):
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mr1 = ((output_drive_strength >> 0) & 1) << 1
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mr1 |= ((output_drive_strength >> 1) & 1) << 5
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mr1 |= ((rtt_nom >> 0) & 1) << 2
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mr1 |= ((rtt_nom >> 1) & 1) << 6
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mr1 |= ((rtt_nom >> 2) & 1) << 9
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return mr1
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def format_mr2(cwl, rtt_wr):
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mr2 = (cwl-5) << 3
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mr2 |= rtt_wr << 9
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return mr2
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mr0 = format_mr0(cl, 8, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK)
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mr1 = format_mr1(1, 1) # Output Drive Strength RZQ/7 (34 ohm) / Rtt RZQ/4 (60 ohm)
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mr2 = format_mr2(sdram_phy_settings.cwl, 2) # Rtt(WR) RZQ/4
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mr3 = 0
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init_sequence = [
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("Release reset", 0x0000, 0, cmds["UNRESET"], 50000),
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 10000),
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("Load Mode Register 2", mr2, 2, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 3", mr3, 3, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 1", mr1, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 0, CL={0:d}, BL={1:d}".format(cl, bl), mr0, 0, cmds["MODE_REGISTER"], 200),
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("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
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]
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# the value of MR1 needs to be modified during write leveling
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r += "#define DDR3_MR1 {}\n\n".format(mr1)
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else:
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raise NotImplementedError("Unsupported memory type: "+sdram_phy_settings.memtype)
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r += "static void init_sequence(void)\n{\n"
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for comment, a, ba, cmd, delay in init_sequence:
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r += "\t/* {0} */\n".format(comment)
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r += "\tsdram_dfii_pi0_address_write({0:#x});\n".format(a)
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r += "\tsdram_dfii_pi0_baddress_write({0:d});\n".format(ba)
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if cmd[:12] == "DFII_CONTROL":
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r += "\tsdram_dfii_control_write({0});\n".format(cmd)
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else:
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r += "\tcommand_p0({0});\n".format(cmd)
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if delay:
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r += "\tcdelay({0:d});\n".format(delay)
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r += "\n"
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r += "}\n"
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r += "#endif\n"
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return r
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