Greg Davill 5faddcdb50 soc.jtag.ecp5: Support all ECP5 devices ... - "LFE5UM" devices exclude these without serdes		2021-10-27 20:36:31 +10:30
..
cores	soc.jtag.ecp5: Support all ECP5 devices	2021-10-27 20:36:31 +10:30
doc	doc: Fix doc build with Sphinx v1.x	2021-02-04 09:40:04 +01:00
integration	soc/build: Avoid no_we mode on RAMs and move specialization of Efinix memories to fhdl.	2021-10-25 19:08:09 +02:00
interconnect	soc/build: Avoid no_we mode on RAMs and move specialization of Efinix memories to fhdl.	2021-10-25 19:08:09 +02:00
software	Change to common isr handler	2021-10-19 07:14:36 +05:30
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00