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Build your hardware, easily!
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Florent Kermarrec 97cca81e0c tb_TriggerCsr.py : use truth table generator for Sum Lut
2012-08-26 15:44:43 +02:00
migScope add truth table generator 2012-08-26 15:15:44 +02:00
sim tb_TriggerCsr.py : use truth table generator for Sum Lut 2012-08-26 15:44:43 +02:00
spi2Csr tb_spi2Csr: Add clk_ratio 2012-08-26 13:03:11 +02:00
README new library spi2Csr (skeleton) 2012-08-13 01:02:38 +02:00
top.py add truth table generator 2012-08-26 15:15:44 +02:00

README 

[> migScope
------------

This is a small Logic Analyser to be embedded in a Fpga design to debug internal
or external signals.

[> Status:
Early development phase

[> Contact
E-mail: florent@enjoy-digital.fr