bunnie 282f22f09e Add tracelength report generation by default to help with board layout		2017-12-27 22:40:39 +08:00
..
boards	boards/platforms/tinyfpga_b: add defaut serial pins	2017-12-27 00:26:30 +01:00
build	Add tracelength report generation by default to help with board layout	2017-12-27 22:40:39 +08:00
gen	gen/fhdl/verilog: revert _printcomb_simulation and _printcomb_regular (needed for icarus simulation) and add Finish command	2017-09-13 13:47:25 +02:00
soc	soc/integration/soc_core: add uart_name parameters (allow selecting uart without modifications in platform file)	2017-12-26 18:11:47 +01:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00