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90 lines
3.1 KiB
Python
90 lines
3.1 KiB
Python
# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from migen import *
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from migen.fhdl.specials import Tristate
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from litex.soc.interconnect.csr import *
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# I2C Master Bit-Banging ---------------------------------------------------------------------------
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class I2CMaster(Module, AutoCSR):
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"""I2C Master Bit-Banging
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Provides the minimal hardware to do software I2C Master bit banging.
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On the same write CSRStorage (_w), software can control SCL (I2C_SCL), SDA direction and value
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(I2C_OE, I2C_W). Software get back SDA value with the read CSRStatus (_r).
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"""
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pads_layout = [("scl", 1), ("sda", 1)]
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def __init__(self, pads=None):
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if pads is None:
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pads = Record(self.pads_layout)
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self.pads = pads
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self._w = CSRStorage(fields=[
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CSRField("scl", size=1, offset=0),
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CSRField("oe", size=1, offset=1),
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CSRField("sda", size=1, offset=2)],
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name="w")
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self._r = CSRStatus(fields=[
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CSRField("sda", size=1, offset=0)],
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name="r")
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# # #
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_sda_w = Signal()
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_sda_oe = Signal()
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_sda_r = Signal()
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self.comb += [
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pads.scl.eq(self._w.fields.scl),
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_sda_oe.eq( self._w.fields.oe),
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_sda_w.eq( self._w.fields.sda),
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self._r.fields.sda.eq(_sda_r),
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]
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self.specials += Tristate(pads.sda, _sda_w, _sda_oe, _sda_r)
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# SPI Master Bit-Banging ---------------------------------------------------------------------------
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class SPIMaster(Module, AutoCSR):
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"""3/4-wire SPI Master Bit-Banging
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Provides the minimal hardware to do software 3/4-wire SPI Master bit banging.
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On the same write CSRStorage (_w), software can control CLK (SPI_CLK), MOSI (SPI_MOSI), MOSI
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direction (SPI_OE) in the case 3-wire SPI and up to 4 Chip Selects (SPI_CS). Software get back
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MISO (SPI_MISO) with the read CSRStatus (_r).
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"""
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pads_layout = [("clk", 1), ("cs_n", 4), ("mosi", 1), ("miso", 1)]
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def __init__(self, pads=None):
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if pads is None:
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pads = Record(self.pads_layout)
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self.pads = pads
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assert len(pads.cs_n) <= 4
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self._w = CSRStorage(fields=[
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CSRField("clk", size=1, offset=0),
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CSRField("mosi", size=1, offset=1),
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CSRField("oe", size=1, offset=2),
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CSRField("cs", size=1, offset=4)],
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name="w")
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self._r = CSRStatus(fields=[
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CSRField("miso", size=1, offset=0),
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CSRField("mosi", size=1, offset=1)],
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name="r")
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# # #
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_mosi_w = Signal()
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_mosi_oe = Signal()
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_mosi_r = Signal()
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_cs = Signal(4)
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self.comb += [
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pads.clk.eq( self._w.fields.clk),
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_mosi_w.eq( self._w.fields.mosi),
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_mosi_oe.eq( self._w.fields.oe),
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pads.cs_n.eq(~self._w.fields.cs),
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self._r.fields.mosi.eq(_mosi_r),
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]
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if hasattr(pads, "miso"):
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self.comb += self._r.fields.miso.eq(pads.miso)
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self.specials += Tristate(pads.mosi, _mosi_w, _mosi_oe, _mosi_r)
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