Florent Kermarrec 9bef218ad6 cpu/microwatt: fix integration/crt0.S (thanks Benjamin Herrenschmidt). ... Tested on Arty A7: __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2020 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on May 4 2020 17:15:13 BIOS CRC passed (0adc4193) Migen git sha1: 5b5e4fd LiteX git sha1: 6f24d46d --=============== SoC ==================-- CPU: Microwatt @ 100MHz ROM: 32KB SRAM: 4KB L2: 8KB MAIN-RAM: 262144KB --========== Initialization ============-- Initializing SDRAM... SDRAM now under software control Read leveling: m0, b0: |00000000000000000000000000000000| delays: - m0, b1: |00000000000000000000000000000000| delays: - m0, b2: |00000000000000000000000000000000| delays: - m0, b3: |00000000000000000000000000000000| delays: - m0, b4: |00000000000000000000000000000000| delays: - m0, b5: |00000000000000000000000000000000| delays: - m0, b6: |00000111111111111100000000000000| delays: 11+-06 m0, b7: |00000000000000000000000000000000| delays: - best: m0, b6 delays: 11+-06 m1, b0: |00000000000000000000000000000000| delays: - m1, b1: |00000000000000000000000000000000| delays: - m1, b2: |00000000000000000000000000000000| delays: - m1, b3: |00000000000000000000000000000000| delays: - m1, b4: |00000000000000000000000000000000| delays: - m1, b5: |10000000000000000000000000000000| delays: 00+-00 m1, b6: |00000011111111111100000000000000| delays: 12+-06 m1, b7: |00000000000000000000000000000000| delays: - best: m1, b6 delays: 12+-06 SDRAM now under hardware control Memtest OK Memspeed Writes: 129Mbps Reads: 215Mbps --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex>		2020-05-04 17:30:50 +02:00
..
cpu	cpu/microwatt: fix integration/crt0.S (thanks Benjamin Herrenschmidt).	2020-05-04 17:30:50 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
bitbang.py	soc/cores/bitbang: fix missing self.comb on miso.	2020-02-25 15:57:14 +01:00
clock.py	diamond: quiet warning about missing clkin freq for EHXPLLL	2020-05-04 01:10:09 -07:00
code_8b10b.py	cores/code_8b10b: set reset_less to True on datapath signals.	2020-04-06 11:35:18 +02:00
dna.py	cores/dna: cleanup and add add_timing_constraints method	2020-01-21 14:08:17 +01:00
ecc.py	soc/cores/ecc: improve readibility, uniformize with others cores	2019-09-29 16:02:04 +02:00
emif.py	cores: add External Memory Interface (EMIF) Wishbone bridge.	2020-04-12 16:34:33 +02:00
freqmeter.py	soc/cores: rename frequency_meter to freqmeter and uniformize with others cores	2019-09-29 16:08:39 +02:00
gpio.py	cores/gpio: add CSR descriptions.	2020-03-11 12:06:15 +01:00
hyperbus.py	litex.build: update from migen.genlib.io litex.build.io.	2020-04-10 09:49:45 +02:00
i2s.py	soc/cores/i2s: fix rst parsing errors	2020-03-10 20:37:55 +08:00
icap.py	soc/cores: use reset_less on datapath/configuration CSRStorages.	2020-04-06 13:17:14 +02:00
identifier.py	soc/cores: uniformize (continue)	2019-09-29 17:04:21 +02:00
jtag.py	soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART)	2019-09-06 11:55:41 +02:00
prbs.py	soc/cores: uniformize (continue)	2019-09-29 17:04:21 +02:00
pwm.py	soc/cores: use reset_less on datapath/configuration CSRStorages.	2020-04-06 13:17:14 +02:00
spi.py	soc/cores/spi: add optional aligned mode.	2020-04-22 13:15:51 +02:00
spi_flash.py	soc/cores: use reset_less on datapath/configuration CSRStorages.	2020-04-06 13:17:14 +02:00
spi_opi.py	Fix off-by-one error on almost full condition for prefetch	2020-03-24 08:04:35 +01:00
timer.py	cores: timer: clean up wording for timer documentation	2020-01-02 16:24:12 +08:00
uart.py	soc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce.	2020-03-31 16:54:38 +02:00
up5kspram.py	cores/up5ksram: optimize bus.adr decoding	2019-07-22 07:55:47 +02:00
usb_fifo.py	soc/cores: uniformize (continue)	2019-09-29 17:04:21 +02:00
xadc.py	soc/cores: use reset_less on datapath/configuration CSRStorages.	2020-04-06 13:17:14 +02:00