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Author SHA1 Message Date
Florent Kermarrec
9bef218ad6 cpu/microwatt: fix integration/crt0.S (thanks Benjamin Herrenschmidt). 
Tested on Arty A7:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on May  4 2020 17:15:13
 BIOS CRC passed (0adc4193)

 Migen git sha1: 5b5e4fd
 LiteX git sha1: 6f24d46d

--=============== SoC ==================--
CPU:       Microwatt @ 100MHz
ROM:       32KB
SRAM:      4KB
L2:        8KB
MAIN-RAM:  262144KB

--========== Initialization ============--
Initializing SDRAM...
SDRAM now under software control
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |00000000000000000000000000000000| delays: -
m0, b5: |00000000000000000000000000000000| delays: -
m0, b6: |00000111111111111100000000000000| delays: 11+-06
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b6 delays: 11+-06
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |00000000000000000000000000000000| delays: -
m1, b5: |10000000000000000000000000000000| delays: 00+-00
m1, b6: |00000011111111111100000000000000| delays: 12+-06
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b6 delays: 12+-06
SDRAM now under hardware control
Memtest OK
Memspeed Writes: 129Mbps Reads: 215Mbps

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2020-05-04 17:30:50 +02:00
shuffle2
ee413527ac
diamond: quiet warning about missing clkin freq for EHXPLLL 
FREQUENCY_PIN_CLKI should be given in mhz
 2020-05-04 01:10:09 -07:00
Florent Kermarrec
2112703181 cpu/microwatt: add powerpc64le-linux-gnu to gcc_triple. 
It seems to be what most distros cross-comiplers are using.
 2020-05-04 08:51:38 +02:00
Florent Kermarrec
c06a127909 cpu/microwatt: add pythondata and fix build with it. 2020-05-04 08:46:25 +02:00
Florent Kermarrec
45377d9faa cpus: use a common definition of gcc_triple for the RISC-V CPUs, reorganize CPU by ISA/Data-Width. 2020-05-03 21:29:54 +02:00
Florent Kermarrec
b02053357c cpu/vexriscv: fix flush_cpu_icache, remove workaround on boot.c. 2020-05-02 20:07:52 +02:00
Florent Kermarrec
97e534d0b6 cpus: add nop instruction and use it to simplify the BIOS. 2020-05-02 12:52:25 +02:00
Florent Kermarrec
4efc783534 cpus: add human_name attribute and use it to simplify the BIOS. 2020-05-02 11:52:58 +02:00
Sadullah Canakci
0c770e0683 Update README.md 2020-05-02 02:51:41 -04:00
sadullah
19bb1b9b8c update to comply with python-data layout 2020-05-01 23:44:20 -04:00
sadullah
3eb9efd64f BP fpga recent version 2020-05-01 16:27:30 -04:00
sadullah
bf864d335b Fix memory transducer bug, --with-sdram for BIOS works, memspeed works 2020-05-01 16:27:27 -04:00
sadullah
cf01ea65f3 rebased, minor changes in core.py 2020-05-01 16:25:01 -04:00
sadullah
b7b9a1f0fb Linux works, LiteDRAM works (need cleaning, temporary push) 2020-05-01 16:24:58 -04:00
Sadullah Canakci
74140587c8 Create GETTING STARTED 
Rename GETTING STARTED to GETTING STARTED.md

Update GETTING STARTED.md

Update GETTING STARTED.md

Update GETTING STARTED.md
 2020-05-01 16:20:35 -04:00
Florent Kermarrec
bd8a410047 cpu/minerva: add pythondata and use it to compile the sources. 2020-05-01 20:12:02 +02:00
Florent Kermarrec
3c70c83f9b cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs. 2020-05-01 12:41:14 +02:00
Florent Kermarrec
bb70a2325a cpu/software: move CPU specific software from the BIOS to the CPU directories. 
This simplifies the integration of the CPUs' software, avoid complex switches in the code,
and is a first step to make CPUs fully pluggable.

The CPU name is no longer present in the crt0 files (for example crt0-vexriscv-ctr.o
becomes crt0-ctr.o) so users building firmwares externally will have to update their
Makefiles to remove the $(CPU) from crt0-$(CPU)-ctr.o.
 2020-05-01 11:04:54 +02:00
Florent Kermarrec
0abc7d4f0b cpu/Minerva: Clone the repository locally for now, we need to create a pythondata repository. 2020-05-01 11:03:07 +02:00
Florent Kermarrec
6d0896de1d cpu/serv: switch to pythondata package instead of local git clone. 2020-04-28 10:34:39 +02:00
enjoy-digital
4d86ab9ded
Merge pull request #399 from mithro/litex-sm2py 
Converting LiteX to use Python modules.
 2020-04-28 08:34:19 +02:00
Florent Kermarrec
5ef869b9eb soc/cpu: add memory_buses to cpus and use them in add_sdram. 
This allows the CPU to have direct buses to the memory and replace the Rocket specific code.
 2020-04-27 23:53:52 +02:00
Florent Kermarrec
467fee3e23 soc/cpu: rename cpu.buses to cpu.periph_buses. 2020-04-27 23:08:15 +02:00
enjoy-digital
317ea7edd1
Merge branch 'master' into litex-sm2py 2020-04-27 22:24:10 +02:00
Florent Kermarrec
4dece4ce24 soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case). 2020-04-27 19:06:16 +02:00
Florent Kermarrec
fb9e369a19 serv: connect reset. 2020-04-27 13:26:45 +02:00
Florent Kermarrec
71778ad226 serv: update copyrights (Greg Davill found the typos/issues). 2020-04-27 10:27:44 +02:00
Florent Kermarrec
1f9db583fd serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :). 2020-04-26 21:05:47 +02:00
Florent Kermarrec
2efd939d06 serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill). 2020-04-26 16:26:57 +02:00
Florent Kermarrec
22c3923644 initial SERV integration. 2020-04-23 08:18:41 +02:00
Florent Kermarrec
0b3c4b50fa soc/cores/spi: add optional aligned mode. 
In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
 2020-04-22 13:15:51 +02:00
Florent Kermarrec
6bb22dfe6b cores/spi: simplify. 2020-04-22 12:20:23 +02:00
Florent Kermarrec
4fe31f0760 cores: add External Memory Interface (EMIF) Wishbone bridge. 
Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.
 2020-04-12 16:34:33 +02:00
Tim 'mithro' Ansell
ebcb2a4406 Rename litex-data-XXX-YYY to pythondata-XXX-YYY 2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
e618d41ffb Fixing mor1kx data finding. 2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
1c1c5bcbda Remove submodules. 2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
d5a21a7522 Converting litex to use Python modules. 2020-04-11 18:37:06 -07:00
Florent Kermarrec
79913e8614 litex.build: update from migen.genlib.io litex.build.io. 2020-04-10 09:49:45 +02:00
David Sawatzke
d69b4443b3 Add riscv64-none-elf triple 2020-04-09 05:36:10 +02:00
Florent Kermarrec
14bf8b8190 soc/cores/clock: add Max10PLL. 2020-04-08 08:54:12 +02:00
Florent Kermarrec
2470ef5096 soc/cores/clock: add Cyclone10LPPLL. 2020-04-08 08:33:57 +02:00
Florent Kermarrec
f8d6d0fda8 soc/cores/clock/CycloneVPLL: fix typos. 2020-04-08 08:25:46 +02:00
Florent Kermarrec
970c8de4c2 soc/cores/clock: rename Altera to Intel. 2020-04-08 08:16:37 +02:00
Florent Kermarrec
383fcd36d6 soc/cores/clock: add CycloneVPLL. 2020-04-07 17:24:12 +02:00
Florent Kermarrec
0f17547c5b soc/cores/clock: add initial AlteraClocking/CycloneIV support. 2020-04-07 16:59:53 +02:00
Florent Kermarrec
0f352cd648 soc/cores: use reset_less on datapath/configuration CSRStorages. 2020-04-06 13:17:14 +02:00
Florent Kermarrec
b95965de73 cores/code_8b10b: set reset_less to True on datapath signals. 
Reset is only required on control signals.
 2020-04-06 11:35:18 +02:00
Florent Kermarrec
6043108376 soc/cores/clock/ECP5PLL: add CLKI_DIV support. 2020-04-03 11:14:57 +02:00
Florent Kermarrec
91981b960c soc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce. 
This reduces logic a bit. It does not make large difference on usual design with
only 1 UART, but is interesting on designs with hundreds of UARTs used to "document"
FPGA boards :) (similar to https://github.com/enjoy-digital/camlink_4k/blob/master/ios_stream.py)
 2020-03-31 16:54:38 +02:00
Florent Kermarrec
87160059d3 soc/cores/spi_flash: add ECP5SPIFlash (non-memory-mapped). 2020-03-31 16:17:12 +02:00