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cpu
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serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill).
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2020-04-26 16:26:57 +02:00 |
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__init__.py
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litex: reorganize things, first work working version
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2015-11-07 17:48:55 +01:00 |
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bitbang.py
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soc/cores/bitbang: fix missing self.comb on miso.
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2020-02-25 15:57:14 +01:00 |
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clock.py
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litex.build: update from migen.genlib.io litex.build.io.
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2020-04-10 09:49:45 +02:00 |
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code_8b10b.py
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cores/code_8b10b: set reset_less to True on datapath signals.
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2020-04-06 11:35:18 +02:00 |
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dna.py
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cores/dna: cleanup and add add_timing_constraints method
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2020-01-21 14:08:17 +01:00 |
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ecc.py
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soc/cores/ecc: improve readibility, uniformize with others cores
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2019-09-29 16:02:04 +02:00 |
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emif.py
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cores: add External Memory Interface (EMIF) Wishbone bridge.
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2020-04-12 16:34:33 +02:00 |
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freqmeter.py
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soc/cores: rename frequency_meter to freqmeter and uniformize with others cores
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2019-09-29 16:08:39 +02:00 |
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gpio.py
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cores/gpio: add CSR descriptions.
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2020-03-11 12:06:15 +01:00 |
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hyperbus.py
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litex.build: update from migen.genlib.io litex.build.io.
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2020-04-10 09:49:45 +02:00 |
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i2s.py
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soc/cores/i2s: fix rst parsing errors
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2020-03-10 20:37:55 +08:00 |
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icap.py
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soc/cores: use reset_less on datapath/configuration CSRStorages.
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2020-04-06 13:17:14 +02:00 |
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identifier.py
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soc/cores: uniformize (continue)
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2019-09-29 17:04:21 +02:00 |
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jtag.py
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soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART)
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2019-09-06 11:55:41 +02:00 |
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prbs.py
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soc/cores: uniformize (continue)
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2019-09-29 17:04:21 +02:00 |
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pwm.py
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soc/cores: use reset_less on datapath/configuration CSRStorages.
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2020-04-06 13:17:14 +02:00 |
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spi.py
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soc/cores/spi: add optional aligned mode.
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2020-04-22 13:15:51 +02:00 |
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spi_flash.py
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soc/cores: use reset_less on datapath/configuration CSRStorages.
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2020-04-06 13:17:14 +02:00 |
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spi_opi.py
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Fix off-by-one error on almost full condition for prefetch
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2020-03-24 08:04:35 +01:00 |
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timer.py
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cores: timer: clean up wording for timer documentation
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2020-01-02 16:24:12 +08:00 |
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uart.py
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soc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce.
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2020-03-31 16:54:38 +02:00 |
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up5kspram.py
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cores/up5ksram: optimize bus.adr decoding
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2019-07-22 07:55:47 +02:00 |
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usb_fifo.py
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soc/cores: uniformize (continue)
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2019-09-29 17:04:21 +02:00 |
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xadc.py
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soc/cores: use reset_less on datapath/configuration CSRStorages.
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2020-04-06 13:17:14 +02:00 |
