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388 commits

Author SHA1 Message Date
Florent Kermarrec
cca0478a5e soc/cores/spi: use new CSRField (no functional change) 2019-09-16 17:02:55 +02:00
Florent Kermarrec
80b2bef387 soc/cores/bitbang: use new CSRField (no functional change) 2019-09-16 16:56:00 +02:00
Florent Kermarrec
d0ebbda4b3 soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART) 2019-09-06 11:55:41 +02:00
Florent Kermarrec
a2938a7ae7 soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic" 2019-08-31 18:34:08 +02:00
enjoy-digital
19d3acfc71
Merge pull request #251 from micro-FPGA/master 
atlantic JTAG UART working module
 2019-08-31 18:33:27 +02:00
Antti Lukats
fb00ee85a2 Create atlantic.py 
atlantic JTAG uart for Intel FPGA's, working and tested on Intel C10LP EK
 2019-08-30 09:35:10 +02:00
Florent Kermarrec
41fe7cae0b core/spi: add minimal SPISlave 2019-08-29 09:46:20 +02:00
Florent Kermarrec
4990bf33c0 soc/core: simplify/cleanup HyperRAM core 
- rename core to hyperbus.
- change layout (cs_n with variable length instead of cs0_n, cs1_n).
- use DifferentialOutput when differential clock is used.
- add test (python3 -m unittest test.test_hyperbus).

Usage example:
from litex.soc.cores.hyperbus import HyperRAM
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
 2019-08-16 14:04:58 +02:00
Antti Lukats
d1502d4195 soc/cores: add initial simple hyperram core 2019-08-16 09:48:17 +02:00
Florent Kermarrec
6d5fddc160 cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally) 2019-08-14 07:35:45 +02:00
Florent Kermarrec
e670cb9176 cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus 2019-08-09 12:33:10 +02:00
Florent Kermarrec
0c287b11ba cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap 2019-08-09 09:27:32 +02:00
Florent Kermarrec
d3d0a6231c cores/clock: juse use 1e9/freq instead of period_ns 2019-08-07 08:29:20 +02:00
Florent Kermarrec
a881817fb3 cores/clock/s6pll: add phase support 2019-08-07 08:18:54 +02:00
Florent Kermarrec
6b7ca0cff7 cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq 2019-08-07 08:17:44 +02:00
Florent Kermarrec
236070fdcf cores: -x on spi.py 2019-08-05 10:36:43 +02:00
Florent Kermarrec
ce5c58592b soc/cores/uart: add FT245 FIFO mode support (sync & async) 2019-08-04 12:22:35 +02:00
Florent Kermarrec
92d93ad221 cores/pwm: remove default CSR reset values. 2019-07-29 08:38:28 +02:00
Mateusz Holenko
932475a29b cpu/vexriscv: bump submodule 2019-07-25 08:43:35 +02:00
Mateusz Holenko
3e89c56468 cpu/vexriscv: bump submodule 2019-07-23 11:49:18 +02:00
Florent Kermarrec
0acacbaa82 cores/clock: cleanup 2019-07-23 09:54:30 +02:00
Florent Kermarrec
edf8aa8cfd cores/clock: add initial iCE40 support 2019-07-23 09:27:20 +02:00
Florent Kermarrec
6d54335839 cores/spi_flash/add_clk_primitive: return if clk primitive is not needed 2019-07-22 21:55:07 +02:00
Florent Kermarrec
95cfd0b9e5 cores/spi_flash: add SpiFlashCommon and use it to add clk primitives (7-Series/ECP5 support for now) 2019-07-22 10:28:03 +02:00
Florent Kermarrec
0eff65bb31 cores/up5ksram: optimize bus.adr decoding 2019-07-22 07:55:47 +02:00
Florent Kermarrec
bb99c4685a cores/up5kspram: simplify and add support for all width/depth configurations 2019-07-21 19:28:31 +02:00
Florent Kermarrec
eaf84b8581 cores/pwm: remove clock_domain support (better to use ClockDomainsRenamer), make csr optional 2019-07-20 12:57:32 +02:00
Florent Kermarrec
ea619e3afe cores/spi: rename add_control paramter to add_csr 2019-07-20 12:56:37 +02:00
Francis Lam
c6c743915a soc: cores: fix name of EHXPLLL output clock in ECP5PLL 2019-07-14 12:27:28 -07:00
Florent Kermarrec
d3aaaf5e6c cores/spi: fix/simplify loopback 2019-07-13 13:10:27 +02:00
Florent Kermarrec
769d15d433 cores/spi: move CSR control/status to add_control method, add loopback capability and simple xfer loopback test 
Moving control/status registers to add_control method allow using SPIMaster directly with exposed signals.
Add loopback capability (mostly for simulation, but can be useful on hardware too).
 2019-07-13 12:55:19 +02:00
Florent Kermarrec
ee8fec10ff soc/cores: add ECC (Error Correcting Code) 
Hamming codes with additional parity (SECDED):
- Single Error Correction
- Double Error Detection
 2019-07-13 11:44:29 +02:00
Ilia Sergachev
dacec6aa86 spi: change CSR to CSRStorage 2019-07-12 14:12:51 +02:00
Florent Kermarrec
282ae96354 cores: add simple PWM (Pulse Width Modulation) module 2019-07-05 19:39:08 +02:00
Florent Kermarrec
77e7f9b3c1 core/spi: make cs_n optional (sometimes managed externally) 2019-07-05 19:18:52 +02:00
Florent Kermarrec
e726ad80ac cores/spi_flash: add non-memory mapped S7SPIFlash modules based on SPIMaster (for design were we only want to re-program the bistream) 2019-07-05 19:01:55 +02:00
Florent Kermarrec
4c18c991bc cores: add ICAP core (tested with reconfiguration commands) 2019-07-05 18:30:34 +02:00
Florent Kermarrec
6b82f23ce1 cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time configurable data_width and frequency. 2019-07-05 15:50:58 +02:00
Florent Kermarrec
ada70e8c52 soc/cores/spi: remove too complicated and does not seem reliable in all cases. 2019-07-05 14:38:09 +02:00
Florent Kermarrec
7cd5c0f39b cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging 2019-07-05 14:26:10 +02:00
Florent Kermarrec
d29b841997 cores: remove nor_flash_16 (obsolete, most of the boards are now using SPI flash) 2019-07-05 13:13:31 +02:00
Florent Kermarrec
3f6bd266d9 cores/gpio: remove Blinker 2019-07-05 13:09:21 +02:00
Florent Kermarrec
cef2369015 core/spi_flash: re-integrate bitbang write support 2019-06-25 19:09:30 +02:00
Florent Kermarrec
ecf999b8c7 soc/cores: add usb_fifo with FT245 USB FIFO PHY from LiteUSB, deprecate LiteUSB 
LiteUSB was not up to date was not a real USB PHY but was just providing USB FIFO PHYs.
New true USB cores are now available: Daisho, ValentyUSB, so it's better using
then for true USB support. We only keep the FT245 FIFO PHY in LiteX that can be
useful to interface with USB2/USB3 USB FIFOs.
 2019-06-24 10:58:36 +02:00
Florent Kermarrec
daa4307d9e add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
Tim 'mithro' Ansell
d8ac936206 Convert top level comment to a docstring. 2019-06-21 12:03:30 -07:00
William D. Jones
7656f54d0a soc: cores: add up5kspram module 
The ICE40UP5K has 128 kB of SPRAM that's designed to be used
as memory for a softcore.  This memory is actually 4 16-bit
chunks that we can gang together to give us either 64 kB or
128 kB.

Add a module that will allow us to use this memory in an ICE40.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-06-20 11:12:46 -07:00
Florent Kermarrec
73dbffe8f2 cores/frequency_meter: allow passing clk to be measured as a parameter 2019-06-20 09:03:30 +02:00
Gabriel L. Somlo
f75863fc31 cpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants 2019-06-18 06:46:24 -04:00
Florent Kermarrec
c0df9e0823 cpu/rocket: update submodule 2019-06-18 09:44:13 +02:00
Florent Kermarrec
87118d509c integration/soc_core: move cpu_variant checks/formating to cpu 2019-06-17 09:55:27 +02:00
Florent Kermarrec
f6b67a6dae cpu/vexriscv: add "linux+no-dsp" variant 2019-06-17 09:54:17 +02:00
Florent Kermarrec
95b1b454f4 cpu/vexriscv: update 2019-06-17 09:24:57 +02:00
Florent Kermarrec
243d7c7696 soc/cores: add PRBS (Pseudo Random Binary Sequence) Generator/Checker 
Imported from LiteICLink. PRBS can be useful for different purposes, so is
better integrated in LiteX.
 2019-06-10 16:05:36 +02:00
Florent Kermarrec
1c34b4a015 cpu/vexriscv: update submodule 2019-06-10 12:57:21 +02:00
Florent Kermarrec
850b311d04 cpu/vexriscv: update submodule 2019-06-07 18:36:46 +02:00
Gabriel L. Somlo
019fd94005 fixup: generated-verilog submodule for experimental Rocket support 
FIXME: This patch uses https://github.com/gsomlo/rocket-litex-verilog,
however in the long term it would perhaps be better if enjoy-digital
hosted the generated-verilog repository.
Once that's in place, I'd be happy to re-spin (and squash) this patch
on top of its parent -- GLS
 2019-05-23 18:22:37 -04:00
Gabriel L. Somlo
1a530cf27d soc/cores/cpu/rocket: Support for 64-bit RocketChip (experimental) 
Simulate a Rocket-based 64-bit LiteX SoC with the following command:

  litex/tools/litex_sim.py [--with-sdram] --cpu-type=rocket

NOTE: Synthesizes to FPGA and passes timing at 50MHz on nexys4ddr
(with vivado) and ecp5versa (with yosys/trellis/nextpnr), but at
this time does not yet properly initialize physical on-board DRAM.
On ecp5versa, using '--with-ethernet', up to 97% of the available
TRELLIS_SLICE capacity is utilized.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-05-23 15:59:51 -04:00
Florent Kermarrec
10670e22ac soc/cores/minerva: update to latest 2019-05-17 22:21:57 +02:00
Florent Kermarrec
eb6fa45833 cpu/vexriscv/core: update 2019-05-13 10:59:26 +02:00
Florent Kermarrec
0cad80e935 cpu/vexriscv: update submodule (new linux variant) 2019-05-13 10:59:03 +02:00
Florent Kermarrec
2f2b9b319f soc/cores: remove cordic 
Cordic is useful for DSP cores but not as a Soc building block.
 2019-05-11 09:36:53 +02:00
Florent Kermarrec
47dc87584f integration/soc_core: rework interrupt assignation/reservation 
The CPUs can now reserve specific interrupts with reserved_interrupts property.
User can still define interrupts in SoCCore.interrupt_map (old way) or use
add_interrupt method. Interrupts specific to SoCCore internal modules are
allocated automatically on the remaining free interrupt ids.

Priority for the interrupts allocation:
- 1) CPU reserved interrupts.
- 2) User interrupts.
- 3) SoCCore interrupts.
 2019-05-09 11:54:22 +02:00
Mateusz Holenko
8caa38bc25 cpu: add reserved_interrupts property 2019-05-09 09:00:06 +02:00
David Shah
a048ba47c4 vexriscv: Fix some floating signals 
Signed-off-by: David Shah <dave@ds0.me>
 2019-05-04 17:27:21 +01:00
Florent Kermarrec
5989076346 cores/cpu/vexriscv: add VexRiscvTimer and use it for the linux variant 2019-05-03 09:30:26 +02:00
Florent Kermarrec
dbb71af189 cpu: use property methods to return name, endianness, gcc triple/flags, linker output format 2019-04-29 09:58:51 +02:00
Florent Kermarrec
d828c3a596 cpu: integrate nmigen version of Minerva, add submodule 2019-04-28 23:40:33 +02:00
Kurt Kiefer
bf27869ad9 fix vexriscv build 2019-04-28 11:10:20 +02:00
enjoy-digital
2d5bae3def
Merge pull request #175 from mithro/cpu-docs 
Standardizing `cpu_variants` and adding lots of documentation
 2019-04-27 21:24:06 +02:00
Tim 'mithro' Ansell
39c579baa2 Standardize the cpu_variant strings. 
Current valid `cpu_variant` values;
 * minimal  (alias: min)
 * lite     (alias: light, zephyr, nuttx)
 * standard (alias: std) - Default
 * full     (alias: everything)
 * linux

Fully documented in the [docs/Soft-CPU.md](docs/Soft-CPU.md) file
mirrored from the
[LiteX-BuildEnv Wiki](https://github.com/timvideos/litex-buildenv/wiki).

Also support "extensions" which are added to the `cpu_variant` with a
`+`. Currently only the `debug` extension is supported. In future hope
to add `mmu` and `hmul` extensions.
 2019-04-26 17:44:30 -05:00
Florent Kermarrec
3a2e283613 .gitmodules: use our VexRiscv-verilog 2019-04-27 00:00:55 +02:00
Florent Kermarrec
10cf0fdea3 cores/cpu/vexriscv: fix wrong revert 2019-04-23 11:13:29 +02:00
Florent Kermarrec
40342404f2 cores/clock: add divclk_divide_range on S6PLL/S6DCM 2019-04-23 06:43:48 +02:00
Florent Kermarrec
0d282f38f9 cores/clock: use common XilinxClocking class for all Xilinx clocking modules 2019-04-23 06:35:39 +02:00
Michael Betz
83699ea0a5 cores/clock: add initial Spartan6 PLL/DCM support 2019-04-23 06:23:00 +02:00
Sean Cross
c780fb22b7 Merge branch 'master' of https://github.com/enjoy-digital/litex 2019-04-19 16:47:55 +08:00
Sean Cross
e2cf45b8a9 cpu: vexriscv: allow cpu_reset_address to be overridden 
Allow the cpu_reset_address value to be overridden, for example allowing
it to be a signal.  That way the reset address can be modified after
synthesis, in dual-core or debug situations.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-19 13:04:57 +08:00
Joanna Brozek
40de01bcb0 vexriscv: Add full and full_debug CPU variant 2019-04-17 09:09:35 +02:00
Florent Kermarrec
c252972bef soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale 2019-04-15 11:36:42 +02:00
Florent Kermarrec
f986974d60 soc/cores/clock: improve presentation 2019-04-15 10:57:00 +02:00
Florent Kermarrec
7b88980d06 vexriscv: allow user to use an external variant 2019-03-15 18:16:25 +01:00
Florent Kermarrec
b04a756abb vexriscv/core: fix min variant 2019-03-15 17:49:39 +01:00
Florent Kermarrec
d3ecdd9995 soc/cores/clock: add actual clk_freqs to config 2019-02-14 10:41:27 +01:00
Florent Kermarrec
8344a6a4ef soc/cores/clock: add USIDELAYCTRL 2019-01-22 12:50:05 +01:00
Florent Kermarrec
1b23890e0d soc/cores/clock: allow ClockSignal to be used for clkin 2019-01-16 22:05:52 +01:00
Florent Kermarrec
7c67bac723 soc/cores/cpu/vexriscv: set default variant to None in add_sources 2019-01-09 10:28:24 +01:00
Florent Kermarrec
648015d78e soc/cores/cpu/vexriscv: move verilog variant selection to add_sources 2019-01-09 09:19:40 +01:00
Florent Kermarrec
2581a00380 soc/cores/clock: add Xilinx Ultrascale PLL/MMCM 2019-01-08 13:21:53 +01:00
Florent Kermarrec
9c801fbe50 soc/cores/clock/ECP5PLL: add basic phase support 2018-12-28 15:03:12 +01:00
Florent Kermarrec
fe5cef4294 soc/cores/clock: remove return on S7PLL.create_clkout 2018-12-19 09:14:26 +01:00
Florent Kermarrec
e9f1049200 soc/cores/cpu/vexriscv: add add_debug method for debug variants 2018-12-12 10:01:49 +01:00
Florent Kermarrec
35155e5172 soc/cores/cpu/vexriscv: add support for the new variants. 2018-12-12 09:39:30 +01:00
Florent Kermarrec
2ace45e6f8 soc/cores/cpu/vexriscv: update submodule 2018-12-12 09:38:53 +01:00
Florent Kermarrec
6d6c2b4c45 soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v) 2018-12-12 09:38:10 +01:00
Florent Kermarrec
18048eb454 cores/clock: test and fix ECP5PLL, phase still not implemented. 2018-11-27 17:24:22 +01:00
Florent Kermarrec
515c06219a cores/clock: add ECP5PLL 2018-11-24 00:47:38 +01:00
Florent Kermarrec
d32e393033 soc/cores/spi_flash: add missing endianness parameter 2018-11-23 18:33:53 +01:00
Florent Kermarrec
b4bdf2a023 cores/clock/S7: just reset the generated clock, not the PLL/MMCM 2018-11-13 14:47:04 +01:00
Florent Kermarrec
af95028574 cpu/mor1kx: use clang only for linux variant 2018-11-13 11:09:39 +01:00
enjoy-digital
4cdd679908
Merge pull request #123 from cr1901/prv32-min 
PicoRV32 Enhancements
 2018-11-01 10:45:32 +01:00
William D. Jones
f32121e0e1 cpu/picorv32: IRQ vector needs to be moved to 16 bytes after the RESET vector. 2018-11-01 02:23:01 -04:00
Florent Kermarrec
f7969b660a cores/clock: add with_reset parameter (default to True) 
In some cases we want to generate the reset externally.
 2018-10-31 16:23:23 +01:00
William D. Jones
f69bd877b9 cpu/picorv32: Create minimal variant (disable mul/div insns, most speed optimizations). 2018-10-30 06:00:45 -04:00
William D. Jones
d05fe673a0 cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs. 2018-10-30 06:00:45 -04:00
Florent Kermarrec
468780c045 soc/cores/spi_flash: add endianness parameter 2018-10-30 10:19:21 +01:00
enjoy-digital
b200ce9983
Merge branch 'master' into xilinx+yosys 2018-10-28 14:59:03 +01:00
Tim 'mithro' Ansell
ba0dd5728e uart: Enable buffering the FIFO. 
On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in
block RAM rather than consuming a large amount of resources.
 2018-10-27 16:04:58 -07:00
Florent Kermarrec
ab8cf3e345 soc/cores/clock: add margin parameter to create_clkout (default = 1%) 2018-10-16 14:57:37 +02:00
Tim 'mithro' Ansell
d13ac3b3d5 cpu/mor1kx: Adding verilog include directory. 2018-10-03 21:57:24 -07:00
Florent Kermarrec
948527b0fe cores/cpu: revert vexriscv (it seems there is a regression in last version) 2018-10-02 12:30:11 +02:00
Florent Kermarrec
934a5da559 soc/cores/clock: add expose_drp on S7PLL/S7MMCM 2018-09-28 13:02:10 +02:00
Florent Kermarrec
74e74dc0e7 soc/cores/clock: different clkin_freq_range for pll and mmcm 2018-09-25 09:09:47 +02:00
Florent Kermarrec
91d8cc2d6a soc/cores/clock: different vco_freq_range for pll and mmcm 2018-09-25 09:04:38 +02:00
Florent Kermarrec
6cd954940c soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG) 2018-09-25 08:36:18 +02:00
Florent Kermarrec
912ca3236b soc/cores/clock: create specific S7IDELAYCTRL module 2018-09-24 23:22:59 +02:00
Florent Kermarrec
baec87f530 soc/cores/clock: add S7MMCM support 2018-09-24 23:20:12 +02:00
Florent Kermarrec
ef40524924 soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest) 2018-09-24 22:58:23 +02:00
Florent Kermarrec
63fc395006 soc/cores: init clock abstraction module 2018-09-24 22:49:01 +02:00
Florent Kermarrec
b528a005a0 cores/cpu: add software informations to cpu and simplify cpu_interface 2018-09-24 07:51:41 +02:00
Florent Kermarrec
07e4c183cd cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise) 2018-09-12 06:02:23 +02:00
Florent Kermarrec
fb24ac0ecc cpu/minerva: add workaround on import until code is released 2018-09-06 16:40:30 +02:00
Jean-François Nguyen
8f377307d8 add Minerva support 2018-09-05 22:33:04 +02:00
William D. Jones
ed507d618d Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly. 2018-09-03 19:48:19 -04:00
Florent Kermarrec
2eeccc5054 vexriscv: update 2018-08-21 11:04:15 +02:00
Florent Kermarrec
4225c3b87c update Vexriscv 2018-08-18 14:14:00 +02:00
Florent Kermarrec
8a69a47e7b cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) 2018-08-17 08:32:32 +02:00
Florent Kermarrec
580efecc8c picorv32: add reset signal 2018-08-07 08:59:34 +02:00
Florent Kermarrec
c0989f65dd soc/cores/cpu: add reset signal 2018-08-06 12:19:23 +02:00
Sean Cross
f17b8324d4 vexriscv: reset wishbone bus on CPU reset 
If the CPU is resetting during a Wishbone transfer, assert the ERR line.

Because the resetOut line is likely multiple cycles long, this should
give Wishbone enough time to finish its transfer, which will cause d.stb
and i.stb to go to 0, which will return d_err and i_err to 0.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-27 15:24:43 +08:00
Sean Cross
c87ca4f1c3 vexriscv: put debug bus directly on wishbone bus 
By placing the VexRiscv debug bus on the Wishbone bus, the Etherbone
core can access 32-bit values directly from the core.  Additionally,
both reading and writing are supported without the need to do a SYNC
register as before.

Additionally, the address of the Wishbone bus won't move around anymore,
as it's fixed when doing `self.register_mem()`.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-27 15:24:43 +08:00
Florent Kermarrec
7dbd85a842 soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx) 2018-07-10 22:32:51 +02:00
Sean Cross
be8eb5ff84 vexriscv: debug: fix reading DATA register 
The REFRESH register accepts an 8-bit address and determines which
register to refresh.  Since there are only two addresses currently in
use, this register can be either 0x00 or 0x04.

A refactor replaced the compare with one that checked for any 0 bits.
Since both 0x00 and 0x04 have 0 bits, this check always evaluated as
true, causing the logic to always refresh the CORE register.

Replace this check with an explicit check for 0x00.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-06 18:22:32 +08:00
Florent Kermarrec
c821a0feab cores/cpu/vexriscv: create variants: None and "debug", some cleanup 2018-07-05 17:31:23 +02:00
Florent Kermarrec
59fa71593d core/cpu/vexriscv/core: improve indentation 2018-07-05 16:51:40 +02:00
Sean Cross
e7c762c8c3 soc: vexriscv: add cpu debug support 
Add support for debugging the CPU, and gate it behind a new cpu_debug
parameter.  With this enabled, a simple Wishbone interface is provided.

The debug version of the core adds two 32-bit registers to the CPU.
The register at address 0 indicates status, and is used to halt
and reset the core.

The debug register at address 4 is used to inject opcodes into the
core, and read back the result.

A patched version of OpenOCD can be used to attach to this bus via
the Litex Ethernet or UART bridges.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-05 17:25:28 +08:00
Sean Cross
2024542a3c vexriscv: verilog: pull debug-enabled verilog 
The upstream vexriscv repo now generates both the current VexRiscv.v
softcore, as well as VexRiscv-Debug.v.  This -Debug varient exposes
their specialized debug bus that allows for attaching a modified version
of openocd.

Sync the litex repo with the upstream version to take advantage of debug
support.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-05 17:25:27 +08:00
Florent Kermarrec
9e737d3c57 soc/cores/code_8b10b: update (from misoc) 2018-06-29 14:24:44 +02:00
Florent Kermarrec
3e723d152a soc/cores/cpu: add add_sources static method 
When creating SoC with multiple sub-SoC already generated, we need an
easy way to add cpu sources.
 2018-06-12 10:54:20 +02:00
Dolu1990
66229c8c05 add VexRiscv support (imported/adapted from misoc) 2018-05-09 15:03:37 +02:00
Florent Kermarrec
f60da4a5dc add VexRiscv submodule 2018-05-09 14:39:31 +02:00
Florent Kermarrec
1925ba176f replace litex.gen imports with migen imports 2018-02-23 13:38:19 +01:00
Sergiusz Bazanski
7ea5a26734 Enable hardware multiplier and divider in PicoRV32 
This should become tunable later once we can configure whether we link
in the soft mul library or not.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
20ed23443b Export trap signal from PicoRV32. 
This is useful for handling crashes from hardware.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
b0be563012 Bump PicoRV32 version. 2018-01-22 18:50:26 +00:00
Felix Held
6318a2b29a Fix all remaining indentation issues in python code 
I ran a script that shouldn't have missed any tab in the python source files.
 2018-01-13 13:19:36 +11:00
Tim 'mithro' Ansell
44650dffd8 cpu: Adding "variant" support. 
It is useful to support slightly different variants of the CPU
configurations. This adds a "cpu_variant" option.

For the mor1k we now have the default mor1k configuration and the
"linux" variant which enables the features needed for Linux support on
the mor1k.

Currently there are no variants for the lm32, but we will likely add a
"tiny" variant for usage on the iCE40.
 2017-12-30 01:18:51 +01:00
Florent Kermarrec
b31d0f37db cpu/picorv32: adapt to current version, some cleanup 2017-12-10 03:01:53 +01:00
Florent Kermarrec
4239aff68a cpu: cleanup wrappers 2017-12-10 02:52:01 +01:00
Florent Kermarrec
ba1bf20f37 soc/cores: add cordic 2017-09-29 12:07:43 +02:00
Florent Kermarrec
c02de1632b soc/cores: fix vivado issue with SPIRegister (at least with Vivado 2017.x+, mosi was not generated correctly), create cs_n signal if pads does not exists 2017-07-27 18:22:01 +02:00
Florent Kermarrec
bdea4152e3 soc/core/uart: add UartStub to enable fast simulation with cpu 2017-07-06 19:19:10 +02:00
Florent Kermarrec
1364ac3657 soc/cores/identifier: append 0 to contents to indicate end of string 2017-06-22 17:53:19 +02:00
Florent Kermarrec
c19c4b711b soc/cores/identifier: remove additionnal first character 2017-06-08 14:15:27 +02:00
Florent Kermarrec
77732fca95 soc/cores/uart: add uart multiplexer 2017-06-05 19:36:30 +02:00
Florent Kermarrec
85aea62d74 soc/core: add frequency meter 2017-06-01 00:39:19 +02:00
Florent Kermarrec
4bc6cf6165 soc/cores: dna/xadc: add missing copyright 2017-05-16 21:18:32 +02:00
Florent Kermarrec
9350a7b5e6 soc/cores: add dna and xadc (for 7-series, add support for others fpgas?) 2017-05-16 21:02:33 +02:00
Florent Kermarrec
b34f74397a soc/cores: add code_8b10b from misoc 2017-04-19 11:05:21 +02:00
Florent Kermarrec
9cfc594280 soc/cores: move flash cores to cores directory 2017-04-19 10:58:15 +02:00
Florent Kermarrec
e1319924aa soc: move uart to a single file 2017-04-19 10:37:59 +02:00
Florent Kermarrec
1acca39397 soc/cores: add new spi master, remove obsolete one 2017-04-19 10:22:35 +02:00
Florent Kermarrec
790020de9f soc/cores/flash/spi_flash: remove bitbanging comment (no longer supported) 2017-02-01 12:21:56 +01:00
Florent Kermarrec
4b77b850ce add SpiFlashSingle and rename SpiFlash to SpiFlashDualQuad 2017-01-26 13:28:18 +01:00
Sebastien Bourdeauducq
e39c470bbc spi_flash: fix bitbang with spi_width=1 2016-12-26 14:11:49 +01:00
Florent Kermarrec
66362b1280 move sdram code to litedram (https://github.com/enjoy-digital/litedram) 2016-04-29 07:45:15 +02:00
Florent Kermarrec
3d98be0997 use new Record.connect omit parameter (replace leave_out) 2016-04-21 09:39:21 +02:00
Florent Kermarrec
5ba03160ed soc/cores: fix spi 2016-04-19 06:49:23 +02:00
Florent Kermarrec
429f533bd0 soc/cores/sdram/settings: simplify modules and fix timing margins computation 2016-04-18 18:22:53 +02:00
Florent Kermarrec
9fa9bdcf68 build/sim: adapt verilator simulation to new stream signals 2016-04-07 08:56:53 +02:00
Florent Kermarrec
17f6cb1f17 initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush) 2016-04-01 00:09:17 +02:00
Florent Kermarrec
b8d89535fd soc/cores/sdram/phy: fix S6QuarterRateDDRPHY 2016-03-29 14:59:30 +02:00
Florent Kermarrec
71a719be44 soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar to AXI) 2016-03-16 20:13:47 +01:00
Florent Kermarrec
e0e2427795 soc: replace all Sink/Source with stream.Endpoint 2016-03-16 18:05:57 +01:00
Florent Kermarrec
0498a31818 some cleanup 
- remove Sink/Source connect specialization.
- remove use of Record.connect
- use sink/source on Buffer
 2015-12-27 13:09:58 +01:00
Florent Kermarrec
1cde84dccf soc/cores/uart remove software (will be re-written and will move to soc/tools) 2015-11-16 17:07:22 +01:00
Florent Kermarrec
7ed2576ce1 soc/integration/cpu_interface: add bases, constants and memories output to csv files 2015-11-15 00:04:44 +01:00
Florent Kermarrec
af909b43d5 soc/cores/uart: add UARTWishboneBridgeDriver software 2015-11-14 21:23:20 +01:00
Florent Kermarrec
a2aa5726bf soc/cores: remove liteeth_mini and use liteeth 2015-11-14 03:22:43 +01:00
Florent Kermarrec
fc3ffe87ac for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00
Florent Kermarrec
525da89c7d soc/interconnect: add wishbonebridge and uart bridge 2015-11-12 00:52:36 +01:00
Florent Kermarrec
1f6983da2c soc/cores/liteeth_mini: add phy model for verilator simulation 2015-11-11 14:22:27 +01:00
Florent Kermarrec
481163b233 soc/cores: reintroduce liteeth_mini (until we switch to liteeth) 2015-11-11 14:01:48 +01:00
Florent Kermarrec
619cd8e695 avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules 2015-11-11 12:10:55 +01:00
Florent Kermarrec
3f43a49382 soc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45990101b 
changes:
-software/bios: remove dataflow
-cores/identifier: replace with user-defined string
-interconnect/CSRBankArray: support read-only mappings
-targets: Added Numato Mimas V2 target
-Our libunwind changes were merged upstream.
-wishbone: update TODO
-replace Counter in Converters
-Fix CSRBankArray
-flterm: properly exit on ^C.
 2015-11-10 16:51:51 +01:00
Florent Kermarrec
3297210e48 boards/targets/sim: get SDRAM working in simulation with sdram/model 2015-11-10 12:57:23 +01:00
Florent Kermarrec
a775672314 litex: get verilator simulation working and add sim target as example 2015-11-07 23:51:37 +01:00
Florent Kermarrec
6a0f85dc42 litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00