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cpu
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soc/cores/cpu/vexriscv: add support for the new variants.
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2018-12-12 09:39:30 +01:00 |
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__init__.py
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litex: reorganize things, first work working version
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2015-11-07 17:48:55 +01:00 |
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clock.py
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cores/clock: test and fix ECP5PLL, phase still not implemented.
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2018-11-27 17:24:22 +01:00 |
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code_8b10b.py
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soc/cores/code_8b10b: update (from misoc)
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2018-06-29 14:24:44 +02:00 |
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cordic.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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dna.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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frequency_meter.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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gpio.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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identifier.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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nor_flash_16.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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spi.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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spi_flash.py
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soc/cores/spi_flash: add missing endianness parameter
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2018-11-23 18:33:53 +01:00 |
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timer.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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uart.py
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uart: Enable buffering the FIFO.
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2018-10-27 16:04:58 -07:00 |
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xadc.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
