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litex/litex/soc/cores
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Florent Kermarrec b8d89535fd soc/cores/sdram/phy: fix S6QuarterRateDDRPHY
2016-03-29 14:59:30 +02:00
..
cpu for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00
flash for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00
sdram soc/cores/sdram/phy: fix S6QuarterRateDDRPHY 2016-03-29 14:59:30 +02:00
spi for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00
uart soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar to AXI) 2016-03-16 20:13:47 +01:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
gpio.py for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00
identifier.py for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00
timer.py for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00