litex/litex/soc/cores
2019-07-22 10:28:03 +02:00
..
cpu
__init__.py
bitbang.py cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging 2019-07-05 14:26:10 +02:00
clock.py soc: cores: fix name of EHXPLLL output clock in ECP5PLL 2019-07-14 12:27:28 -07:00
code_8b10b.py
dna.py
ecc.py
frequency_meter.py add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
gpio.py cores/gpio: remove Blinker 2019-07-05 13:09:21 +02:00
icap.py
identifier.py
prbs.py
pwm.py cores/pwm: remove clock_domain support (better to use ClockDomainsRenamer), make csr optional 2019-07-20 12:57:32 +02:00
spi.py cores/spi: rename add_control paramter to add_csr 2019-07-20 12:56:37 +02:00
spi_flash.py cores/spi_flash: add SpiFlashCommon and use it to add clk primitives (7-Series/ECP5 support for now) 2019-07-22 10:28:03 +02:00
timer.py
uart.py
up5kspram.py cores/up5ksram: optimize bus.adr decoding 2019-07-22 07:55:47 +02:00
usb_fifo.py
xadc.py