soc/cores/cpu/vexriscv: set default variant to None in add_sources

2019-01-09 10:28:24 +01:00 · 2019-01-09 10:28:24 +01:00 · 7c67bac723
parent 648015d78e
commit 7c67bac723
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@ -66,7 +66,7 @@ class LM32(Module):
        self.add_sources(platform, variant)

    @staticmethod
-    def add_sources(platform, variant):
+    def add_sources(platform, variant=None):
        vdir = os.path.join(
            os.path.abspath(os.path.dirname(__file__)), "verilog")
        platform.add_sources(os.path.join(vdir, "submodule", "rtl"),