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soc/cores/cpu/vexriscv: set default variant to None in add_sources

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This commit is contained in:
Florent Kermarrec 2019-01-09 10:28:24 +01:00
parent 648015d78e
commit 7c67bac723
1 changed files with 1 additions and 1 deletions
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2
litex/soc/cores/cpu/lm32/core.py
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@ -66,7 +66,7 @@ class LM32(Module):
self.add_sources(platform, variant)
@staticmethod
def add_sources(platform, variant):
def add_sources(platform, variant=None):
vdir = os.path.join(
os.path.abspath(os.path.dirname(__file__)), "verilog")
platform.add_sources(os.path.join(vdir, "submodule", "rtl"),