| .. |
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cpu
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cpu/vexriscv: bump submodule
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2019-07-25 08:43:35 +02:00 |
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__init__.py
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litex: reorganize things, first work working version
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2015-11-07 17:48:55 +01:00 |
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bitbang.py
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cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging
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2019-07-05 14:26:10 +02:00 |
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clock.py
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cores/clock: juse use 1e9/freq instead of period_ns
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2019-08-07 08:29:20 +02:00 |
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code_8b10b.py
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add CONTRIBUTORS file and add copyright header to all files
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2019-06-23 23:23:56 +02:00 |
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dna.py
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add CONTRIBUTORS file and add copyright header to all files
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2019-06-23 23:23:56 +02:00 |
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ecc.py
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soc/cores: add ECC (Error Correcting Code)
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2019-07-13 11:44:29 +02:00 |
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frequency_meter.py
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add CONTRIBUTORS file and add copyright header to all files
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2019-06-23 23:23:56 +02:00 |
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gpio.py
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cores/gpio: remove Blinker
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2019-07-05 13:09:21 +02:00 |
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icap.py
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cores: add ICAP core (tested with reconfiguration commands)
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2019-07-05 18:30:34 +02:00 |
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identifier.py
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add CONTRIBUTORS file and add copyright header to all files
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2019-06-23 23:23:56 +02:00 |
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prbs.py
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add CONTRIBUTORS file and add copyright header to all files
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2019-06-23 23:23:56 +02:00 |
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pwm.py
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cores/pwm: remove default CSR reset values.
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2019-07-29 08:38:28 +02:00 |
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spi.py
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cores: -x on spi.py
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2019-08-05 10:36:43 +02:00 |
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spi_flash.py
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cores/spi_flash/add_clk_primitive: return if clk primitive is not needed
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2019-07-22 21:55:07 +02:00 |
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timer.py
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add CONTRIBUTORS file and add copyright header to all files
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2019-06-23 23:23:56 +02:00 |
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uart.py
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soc/cores/uart: add FT245 FIFO mode support (sync & async)
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2019-08-04 12:22:35 +02:00 |
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up5kspram.py
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cores/up5ksram: optimize bus.adr decoding
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2019-07-22 07:55:47 +02:00 |
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usb_fifo.py
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soc/cores: add usb_fifo with FT245 USB FIFO PHY from LiteUSB, deprecate LiteUSB
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2019-06-24 10:58:36 +02:00 |
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xadc.py
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
