Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity
4502 commits 42 branches 14 tags 31 MiB
Commit graph

176 commits

Author SHA1 Message Date
Florent Kermarrec
d3d0a6231c cores/clock: juse use 1e9/freq instead of period_ns 2019-08-07 08:29:20 +02:00
Florent Kermarrec
a881817fb3 cores/clock/s6pll: add phase support 2019-08-07 08:18:54 +02:00
Florent Kermarrec
6b7ca0cff7 cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq 2019-08-07 08:17:44 +02:00
Florent Kermarrec
236070fdcf cores: -x on spi.py 2019-08-05 10:36:43 +02:00
Florent Kermarrec
ce5c58592b soc/cores/uart: add FT245 FIFO mode support (sync & async) 2019-08-04 12:22:35 +02:00
Florent Kermarrec
92d93ad221 cores/pwm: remove default CSR reset values. 2019-07-29 08:38:28 +02:00
Mateusz Holenko
932475a29b cpu/vexriscv: bump submodule 2019-07-25 08:43:35 +02:00
Mateusz Holenko
3e89c56468 cpu/vexriscv: bump submodule 2019-07-23 11:49:18 +02:00
Florent Kermarrec
0acacbaa82 cores/clock: cleanup 2019-07-23 09:54:30 +02:00
Florent Kermarrec
edf8aa8cfd cores/clock: add initial iCE40 support 2019-07-23 09:27:20 +02:00
Florent Kermarrec
6d54335839 cores/spi_flash/add_clk_primitive: return if clk primitive is not needed 2019-07-22 21:55:07 +02:00
Florent Kermarrec
95cfd0b9e5 cores/spi_flash: add SpiFlashCommon and use it to add clk primitives (7-Series/ECP5 support for now) 2019-07-22 10:28:03 +02:00
Florent Kermarrec
0eff65bb31 cores/up5ksram: optimize bus.adr decoding 2019-07-22 07:55:47 +02:00
Florent Kermarrec
bb99c4685a cores/up5kspram: simplify and add support for all width/depth configurations 2019-07-21 19:28:31 +02:00
Florent Kermarrec
eaf84b8581 cores/pwm: remove clock_domain support (better to use ClockDomainsRenamer), make csr optional 2019-07-20 12:57:32 +02:00
Florent Kermarrec
ea619e3afe cores/spi: rename add_control paramter to add_csr 2019-07-20 12:56:37 +02:00
Francis Lam
c6c743915a soc: cores: fix name of EHXPLLL output clock in ECP5PLL 2019-07-14 12:27:28 -07:00
Florent Kermarrec
d3aaaf5e6c cores/spi: fix/simplify loopback 2019-07-13 13:10:27 +02:00
Florent Kermarrec
769d15d433 cores/spi: move CSR control/status to add_control method, add loopback capability and simple xfer loopback test 
Moving control/status registers to add_control method allow using SPIMaster directly with exposed signals.
Add loopback capability (mostly for simulation, but can be useful on hardware too).
 2019-07-13 12:55:19 +02:00
Florent Kermarrec
ee8fec10ff soc/cores: add ECC (Error Correcting Code) 
Hamming codes with additional parity (SECDED):
- Single Error Correction
- Double Error Detection
 2019-07-13 11:44:29 +02:00
Ilia Sergachev
dacec6aa86 spi: change CSR to CSRStorage 2019-07-12 14:12:51 +02:00
Florent Kermarrec
282ae96354 cores: add simple PWM (Pulse Width Modulation) module 2019-07-05 19:39:08 +02:00
Florent Kermarrec
77e7f9b3c1 core/spi: make cs_n optional (sometimes managed externally) 2019-07-05 19:18:52 +02:00
Florent Kermarrec
e726ad80ac cores/spi_flash: add non-memory mapped S7SPIFlash modules based on SPIMaster (for design were we only want to re-program the bistream) 2019-07-05 19:01:55 +02:00
Florent Kermarrec
4c18c991bc cores: add ICAP core (tested with reconfiguration commands) 2019-07-05 18:30:34 +02:00
Florent Kermarrec
6b82f23ce1 cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time configurable data_width and frequency. 2019-07-05 15:50:58 +02:00
Florent Kermarrec
ada70e8c52 soc/cores/spi: remove too complicated and does not seem reliable in all cases. 2019-07-05 14:38:09 +02:00
Florent Kermarrec
7cd5c0f39b cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging 2019-07-05 14:26:10 +02:00
Florent Kermarrec
d29b841997 cores: remove nor_flash_16 (obsolete, most of the boards are now using SPI flash) 2019-07-05 13:13:31 +02:00
Florent Kermarrec
3f6bd266d9 cores/gpio: remove Blinker 2019-07-05 13:09:21 +02:00
Florent Kermarrec
cef2369015 core/spi_flash: re-integrate bitbang write support 2019-06-25 19:09:30 +02:00
Florent Kermarrec
ecf999b8c7 soc/cores: add usb_fifo with FT245 USB FIFO PHY from LiteUSB, deprecate LiteUSB 
LiteUSB was not up to date was not a real USB PHY but was just providing USB FIFO PHYs.
New true USB cores are now available: Daisho, ValentyUSB, so it's better using
then for true USB support. We only keep the FT245 FIFO PHY in LiteX that can be
useful to interface with USB2/USB3 USB FIFOs.
 2019-06-24 10:58:36 +02:00
Florent Kermarrec
daa4307d9e add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
Tim 'mithro' Ansell
d8ac936206 Convert top level comment to a docstring. 2019-06-21 12:03:30 -07:00
William D. Jones
7656f54d0a soc: cores: add up5kspram module 
The ICE40UP5K has 128 kB of SPRAM that's designed to be used
as memory for a softcore.  This memory is actually 4 16-bit
chunks that we can gang together to give us either 64 kB or
128 kB.

Add a module that will allow us to use this memory in an ICE40.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-06-20 11:12:46 -07:00
Florent Kermarrec
73dbffe8f2 cores/frequency_meter: allow passing clk to be measured as a parameter 2019-06-20 09:03:30 +02:00
Gabriel L. Somlo
f75863fc31 cpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants 2019-06-18 06:46:24 -04:00
Florent Kermarrec
c0df9e0823 cpu/rocket: update submodule 2019-06-18 09:44:13 +02:00
Florent Kermarrec
87118d509c integration/soc_core: move cpu_variant checks/formating to cpu 2019-06-17 09:55:27 +02:00
Florent Kermarrec
f6b67a6dae cpu/vexriscv: add "linux+no-dsp" variant 2019-06-17 09:54:17 +02:00
Florent Kermarrec
95b1b454f4 cpu/vexriscv: update 2019-06-17 09:24:57 +02:00
Florent Kermarrec
243d7c7696 soc/cores: add PRBS (Pseudo Random Binary Sequence) Generator/Checker 
Imported from LiteICLink. PRBS can be useful for different purposes, so is
better integrated in LiteX.
 2019-06-10 16:05:36 +02:00
Florent Kermarrec
1c34b4a015 cpu/vexriscv: update submodule 2019-06-10 12:57:21 +02:00
Florent Kermarrec
850b311d04 cpu/vexriscv: update submodule 2019-06-07 18:36:46 +02:00
Gabriel L. Somlo
019fd94005 fixup: generated-verilog submodule for experimental Rocket support 
FIXME: This patch uses https://github.com/gsomlo/rocket-litex-verilog,
however in the long term it would perhaps be better if enjoy-digital
hosted the generated-verilog repository.
Once that's in place, I'd be happy to re-spin (and squash) this patch
on top of its parent -- GLS
 2019-05-23 18:22:37 -04:00
Gabriel L. Somlo
1a530cf27d soc/cores/cpu/rocket: Support for 64-bit RocketChip (experimental) 
Simulate a Rocket-based 64-bit LiteX SoC with the following command:

  litex/tools/litex_sim.py [--with-sdram] --cpu-type=rocket

NOTE: Synthesizes to FPGA and passes timing at 50MHz on nexys4ddr
(with vivado) and ecp5versa (with yosys/trellis/nextpnr), but at
this time does not yet properly initialize physical on-board DRAM.
On ecp5versa, using '--with-ethernet', up to 97% of the available
TRELLIS_SLICE capacity is utilized.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-05-23 15:59:51 -04:00
Florent Kermarrec
10670e22ac soc/cores/minerva: update to latest 2019-05-17 22:21:57 +02:00
Florent Kermarrec
eb6fa45833 cpu/vexriscv/core: update 2019-05-13 10:59:26 +02:00
Florent Kermarrec
0cad80e935 cpu/vexriscv: update submodule (new linux variant) 2019-05-13 10:59:03 +02:00
Florent Kermarrec
2f2b9b319f soc/cores: remove cordic 
Cordic is useful for DSP cores but not as a Soc building block.
 2019-05-11 09:36:53 +02:00