litex/migen/bus
Sebastien Bourdeauducq 3fae6c8f03 Do not use super() 2012-12-18 14:54:33 +01:00
..
__init__.py CSR bus definitions 2011-12-05 00:16:44 +01:00
asmibus.py Replace Signal(bits_for(... with Signal(max=... 2012-11-29 21:53:36 +01:00
csr.py Do not use super() 2012-12-18 14:54:33 +01:00
dfi.py Remove Constant 2012-11-28 23:18:43 +01:00
memory.py bus: memory initiator 2012-11-23 16:22:50 +01:00
simple.py New specification for width and signedness 2012-11-29 21:22:38 +01:00
transactions.py bus/transactions: add busname parameter 2012-11-17 19:36:08 +01:00
wishbone.py Do not use super() 2012-12-18 14:54:33 +01:00
wishbone2asmi.py New specification for width and signedness 2012-11-29 21:22:38 +01:00
wishbone2csr.py bus/csr: configurable data width 2012-08-26 21:19:34 +02:00