Robert Jördens 9d241f8cd3 coding.py: rewrite If() to make verilog more readable		2013-06-30 11:39:47 +02:00
..
actorlib	FSM: new API	2013-06-25 22:17:39 +02:00
bank	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
bus	FSM: new API	2013-06-25 22:17:39 +02:00
fhdl	fhdl/verilog: fix signedness rules for comparison	2013-06-26 22:45:47 +02:00
flow	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
genlib	coding.py: rewrite If() to make verilog more readable	2013-06-30 11:39:47 +02:00
pytholite	pytholite: use eval instead of literal_eval	2013-06-28 19:03:55 +02:00
sim	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00