Sebastien Bourdeauducq d0caa738bd FSM: new API		2013-06-25 22:17:39 +02:00
..
__init__.py	CSR bus definitions	2011-12-05 00:16:44 +01:00
asmibus.py	asmibus: remove port sharing	2013-06-14 18:34:36 +02:00
csr.py	csr/sram: fix reads on high addresses when word_bits != 0	2013-06-03 21:52:23 +02:00
dfi.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
lasmibus.py	lasmi: separate request and data ack to support bankmachine FIFOs (buggy/incomplete)	2013-06-17 23:36:03 +02:00
memory.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
transactions.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
wishbone.py	Make memory ports part of specials	2013-05-28 16:11:34 +02:00
wishbone2asmi.py	FSM: new API	2013-06-25 22:17:39 +02:00
wishbone2csr.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
wishbone2lasmi.py	FSM: new API	2013-06-25 22:17:39 +02:00