302 lines
8.4 KiB
Python
302 lines
8.4 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.size import bits_for, value_bits_sign
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from migen.fhdl.tools import *
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from migen.fhdl.tracer import get_obj_var_name
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from migen.fhdl.verilog import _printexpr as verilog_printexpr
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class Special(HUID):
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def iter_expressions(self):
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for x in []:
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yield x
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def rename_clock_domain(self, old, new):
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for obj, attr, direction in self.iter_expressions():
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rename_clock_domain_expr(getattr(obj, attr), old, new)
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def list_clock_domains(self):
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r = set()
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for obj, attr, direction in self.iter_expressions():
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r |= list_clock_domains_expr(getattr(obj, attr))
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return r
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def list_ios(self, ins, outs, inouts):
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r = set()
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for obj, attr, direction in self.iter_expressions():
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if (direction == SPECIAL_INPUT and ins) \
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or (direction == SPECIAL_OUTPUT and outs) \
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or (direction == SPECIAL_INOUT and inouts):
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signals = list_signals(getattr(obj, attr))
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r.update(signals)
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return r
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class Tristate(Special):
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def __init__(self, target, o, oe, i=None):
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Special.__init__(self)
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self.target = target
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self.o = o
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self.oe = oe
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self.i = i
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def iter_expressions(self):
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for attr, target_context in [
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("target", SPECIAL_INOUT),
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("o", SPECIAL_INPUT),
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("oe", SPECIAL_INPUT),
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("i", SPECIAL_OUTPUT)]:
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yield self, attr, target_context
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@staticmethod
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def emit_verilog(tristate, ns):
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def pe(e):
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return verilog_printexpr(ns, e)[0]
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w, s = value_bits_sign(tristate.target)
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r = "assign " + pe(tristate.target) + " = " \
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+ pe(tristate.oe) + " ? " + pe(tristate.o) \
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+ " : " + str(w) + "'bz;\n"
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if tristate.i is not None:
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r += "assign " + pe(tristate.i) + " = " + pe(tristate.target) + ";\n"
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r += "\n"
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return r
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class TSTriple:
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def __init__(self, bits_sign=None, min=None, max=None, reset_o=0, reset_oe=0):
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self.o = Signal(bits_sign, min=min, max=max, reset=reset_o)
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self.oe = Signal(reset=reset_oe)
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self.i = Signal(bits_sign, min=min, max=max)
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def get_tristate(self, target):
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return Tristate(target, self.o, self.oe, self.i)
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class Instance(Special):
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def __init__(self, of, *items, name=""):
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Special.__init__(self)
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self.of = of
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if name:
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self.name_override = name
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else:
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self.name_override = of
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self.items = items
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class _IO:
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def __init__(self, name, expr=None):
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self.name = name
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if expr is None:
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expr = Signal()
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self.expr = expr
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class Input(_IO):
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pass
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class Output(_IO):
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pass
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class InOut(_IO):
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pass
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class Parameter:
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def __init__(self, name, value):
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self.name = name
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self.value = value
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def get_io(self, name):
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for item in self.items:
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if isinstance(item, Instance._IO) and item.name == name:
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return item.expr
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def iter_expressions(self):
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for item in self.items:
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if isinstance(item, Instance.Input):
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yield item, "expr", SPECIAL_INPUT
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elif isinstance(item, Instance.Output):
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yield item, "expr", SPECIAL_OUTPUT
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elif isinstance(item, Instance.InOut):
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yield item, "expr", SPECIAL_INOUT
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@staticmethod
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def emit_verilog(instance, ns):
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r = instance.of + " "
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parameters = list(filter(lambda i: isinstance(i, Instance.Parameter), instance.items))
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if parameters:
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r += "#(\n"
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firstp = True
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for p in parameters:
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if not firstp:
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r += ",\n"
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firstp = False
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r += "\t." + p.name + "("
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if isinstance(p.value, (int, bool)):
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r += verilog_printexpr(ns, p.value)[0]
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elif isinstance(p.value, float):
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r += str(p.value)
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elif isinstance(p.value, str):
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r += "\"" + p.value + "\""
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else:
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raise TypeError
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r += ")"
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r += "\n) "
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r += ns.get_name(instance)
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if parameters: r += " "
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r += "(\n"
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firstp = True
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for p in instance.items:
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if isinstance(p, Instance._IO):
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name_inst = p.name
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name_design = verilog_printexpr(ns, p.expr)[0]
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if not firstp:
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r += ",\n"
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firstp = False
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r += "\t." + name_inst + "(" + name_design + ")"
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if not firstp:
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r += "\n"
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r += ");\n\n"
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return r
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(READ_FIRST, WRITE_FIRST, NO_CHANGE) = range(3)
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class _MemoryPort(Special):
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def __init__(self, adr, dat_r, we=None, dat_w=None,
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async_read=False, re=None, we_granularity=0, mode=WRITE_FIRST,
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clock_domain="sys"):
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Special.__init__(self)
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self.adr = adr
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self.dat_r = dat_r
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self.we = we
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self.dat_w = dat_w
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self.async_read = async_read
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self.re = re
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self.we_granularity = we_granularity
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self.mode = mode
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self.clock = ClockSignal(clock_domain)
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def iter_expressions(self):
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for attr, target_context in [
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("adr", SPECIAL_INPUT),
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("we", SPECIAL_INPUT),
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("dat_w", SPECIAL_INPUT),
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("re", SPECIAL_INPUT),
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("dat_r", SPECIAL_OUTPUT),
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("clock", SPECIAL_INPUT)]:
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yield self, attr, target_context
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@staticmethod
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def emit_verilog(port, ns):
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return "" # done by parent Memory object
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class Memory(Special):
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def __init__(self, width, depth, init=None, name=None):
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Special.__init__(self)
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self.width = width
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self.depth = depth
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self.ports = []
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self.init = init
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self.name_override = get_obj_var_name(name, "mem")
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def get_port(self, write_capable=False, async_read=False,
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has_re=False, we_granularity=0, mode=WRITE_FIRST,
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clock_domain="sys"):
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if we_granularity >= self.width:
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we_granularity = 0
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adr = Signal(max=self.depth)
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dat_r = Signal(self.width)
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if write_capable:
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if we_granularity:
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we = Signal(self.width//we_granularity)
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else:
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we = Signal()
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dat_w = Signal(self.width)
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else:
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we = None
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dat_w = None
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if has_re:
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re = Signal()
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else:
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re = None
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mp = _MemoryPort(adr, dat_r, we, dat_w,
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async_read, re, we_granularity, mode,
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clock_domain)
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self.ports.append(mp)
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return mp
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@staticmethod
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def emit_verilog(memory, ns):
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r = ""
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gn = ns.get_name # usable instead of verilog_printexpr as ports contain only signals
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adrbits = bits_for(memory.depth-1)
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r += "reg [" + str(memory.width-1) + ":0] " \
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+ gn(memory) \
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+ "[0:" + str(memory.depth-1) + "];\n"
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adr_regs = {}
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data_regs = {}
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for port in memory.ports:
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if not port.async_read:
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if port.mode == WRITE_FIRST and port.we is not None:
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adr_reg = Signal(name_override="memadr")
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r += "reg [" + str(adrbits-1) + ":0] " \
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+ gn(adr_reg) + ";\n"
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adr_regs[id(port)] = adr_reg
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else:
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data_reg = Signal(name_override="memdat")
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r += "reg [" + str(memory.width-1) + ":0] " \
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+ gn(data_reg) + ";\n"
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data_regs[id(port)] = data_reg
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for port in memory.ports:
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r += "always @(posedge " + gn(port.clock) + ") begin\n"
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if port.we is not None:
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if port.we_granularity:
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n = memory.width//port.we_granularity
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for i in range(n):
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m = i*port.we_granularity
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M = (i+1)*port.we_granularity-1
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sl = "[" + str(M) + ":" + str(m) + "]"
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r += "\tif (" + gn(port.we) + "[" + str(i) + "])\n"
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r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "]" + sl + " <= " + gn(port.dat_w) + sl + ";\n"
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else:
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r += "\tif (" + gn(port.we) + ")\n"
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r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "] <= " + gn(port.dat_w) + ";\n"
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if not port.async_read:
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if port.mode == WRITE_FIRST and port.we is not None:
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rd = "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n"
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else:
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bassign = gn(data_regs[id(port)]) + " <= " + gn(memory) + "[" + gn(port.adr) + "];\n"
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if port.mode == READ_FIRST or port.we is None:
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rd = "\t" + bassign
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elif port.mode == NO_CHANGE:
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rd = "\tif (!" + gn(port.we) + ")\n" \
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+ "\t\t" + bassign
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if port.re is None:
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r += rd
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else:
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r += "\tif (" + gn(port.re) + ")\n"
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r += "\t" + rd.replace("\n\t", "\n\t\t")
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r += "end\n\n"
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for port in memory.ports:
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if port.async_read:
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r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(port.adr) + "];\n"
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else:
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if port.mode == WRITE_FIRST and port.we is not None:
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r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(adr_regs[id(port)]) + "];\n"
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else:
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r += "assign " + gn(port.dat_r) + " = " + gn(data_regs[id(port)]) + ";\n"
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r += "\n"
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if memory.init is not None:
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r += "initial begin\n"
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for i, c in enumerate(memory.init):
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r += "\t" + gn(memory) + "[" + str(i) + "] <= " + str(memory.width) + "'d" + str(c) + ";\n"
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r += "end\n\n"
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return r
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class SynthesisDirective(Special):
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def __init__(self, template, **signals):
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Special.__init__(self)
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self.template = template
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self.signals = signals
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@staticmethod
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def emit_verilog(directive, ns):
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name_dict = dict((k, ns.get_name(sig)) for k, sig in directive.signals.items())
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formatted = directive.template.format(**name_dict)
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return "// synthesis " + formatted + "\n"
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