103 lines
2.6 KiB
Python
103 lines
2.6 KiB
Python
from migen.fhdl.std import *
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from migen.flow.actor import *
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from migen.genlib.fifo import SyncFIFO
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class Reader(Module):
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def __init__(self, lasmim, fifo_depth=None):
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self.address = Sink([("a", lasmim.aw)])
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self.data = Source([("d", lasmim.dw)])
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self.busy = Signal()
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###
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if fifo_depth is None:
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fifo_depth = lasmim.req_queue_size + lasmim.read_latency + 2
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# request issuance
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request_enable = Signal()
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request_issued = Signal()
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self.comb += [
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lasmim.we.eq(0),
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lasmim.stb.eq(self.address.stb & request_enable),
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lasmim.adr.eq(self.address.a),
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self.address.ack.eq(lasmim.req_ack & request_enable),
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request_issued.eq(lasmim.stb & lasmim.req_ack)
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]
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# FIFO reservation level counter
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# incremented when data is planned to be queued
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# decremented when data is dequeued
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data_dequeued = Signal()
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rsv_level = Signal(max=fifo_depth+1)
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self.sync += [
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If(request_issued,
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If(~data_dequeued, rsv_level.eq(rsv_level + 1))
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).Elif(data_dequeued,
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rsv_level.eq(rsv_level - 1)
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)
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]
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self.comb += [
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self.busy.eq(rsv_level != 0),
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request_enable.eq(rsv_level != fifo_depth)
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]
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# data available
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data_available = lasmim.dat_ack
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for i in range(lasmim.read_latency):
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new_data_available = Signal()
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self.sync += new_data_available.eq(data_available)
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data_available = new_data_available
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# FIFO
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fifo = SyncFIFO(lasmim.dw, fifo_depth)
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self.submodules += fifo
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self.comb += [
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fifo.din.eq(lasmim.dat_r),
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fifo.we.eq(data_available),
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self.data.stb.eq(fifo.readable),
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fifo.re.eq(self.data.ack),
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self.data.d.eq(fifo.dout),
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data_dequeued.eq(self.data.stb & self.data.ack)
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]
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class Writer(Module):
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def __init__(self, lasmim, fifo_depth=None):
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self.address_data = Sink([("a", lasmim.aw), ("d", lasmim.dw)])
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self.busy = Signal()
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###
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if fifo_depth is None:
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fifo_depth = lasmim.req_queue_size + lasmim.write_latency + 2
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fifo = SyncFIFO(lasmim.dw, fifo_depth)
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self.submodules += fifo
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self.comb += [
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lasmim.we.eq(1),
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lasmim.stb.eq(fifo.writable & self.address_data.stb),
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lasmim.adr.eq(self.address_data.a),
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self.address_data.ack.eq(fifo.writable & lasmim.req_ack),
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fifo.we.eq(self.address_data.stb & lasmim.req_ack),
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fifo.din.eq(self.address_data.d)
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]
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data_valid = lasmim.dat_ack
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for i in range(lasmim.write_latency):
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new_data_valid = Signal()
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self.sync += new_data_valid.eq(data_valid),
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data_valid = new_data_valid
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self.comb += [
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fifo.re.eq(data_valid),
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If(data_valid,
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lasmim.dat_we.eq(2**(lasmim.dw//8)-1),
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lasmim.dat_w.eq(fifo.dout)
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),
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self.busy.eq(fifo.readable)
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]
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