litex/migen
Guy Hutchison 9f2f8d279d add hamming-code gen/check lib 2014-11-06 18:19:59 -08:00
..
actorlib actorlib/structuring/Pipeline: make 'busy' a signal 2014-11-01 21:48:02 +08:00
bank remove trailing whitespaces 2014-10-17 17:08:46 +08:00
bus bus/csr: add configurable address_width (needed more than 32 modules with CSR) 2014-11-01 21:22:11 +08:00
fhdl fhdl/verilog: fix tristate to instance connection 2014-10-29 18:18:17 +08:00
flow flow/actor, actorlib/structuring: add packet support 2014-11-01 21:22:46 +08:00
genlib add hamming-code gen/check lib 2014-11-06 18:19:59 -08:00
pytholite remove trailing whitespaces 2014-10-17 17:08:46 +08:00
sim remove trailing whitespaces 2014-10-17 17:08:46 +08:00
test test/test_size: fix slice comparison 2014-11-03 12:08:43 +08:00
util utils/misc: add gcd_multiple function to compute GCD or any number of integers 2013-12-12 17:36:50 +01:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00