55 lines
1.3 KiB
Python
55 lines
1.3 KiB
Python
from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.flow.actor import *
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class Reader(Module):
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def __init__(self):
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self.bus = wishbone.Interface()
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self.address = Sink([("a", 30)])
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self.data = Source([("d", 32)])
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self.busy = Signal()
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###
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bus_stb = Signal()
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data_reg_loaded = Signal()
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data_reg = Signal(32)
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self.comb += [
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self.busy.eq(data_reg_loaded),
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self.bus.we.eq(0),
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bus_stb.eq(self.address.stb & (~data_reg_loaded | self.data.ack)),
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self.bus.cyc.eq(bus_stb),
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self.bus.stb.eq(bus_stb),
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self.bus.adr.eq(self.address.a),
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self.address.ack.eq(self.bus.ack),
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self.data.stb.eq(data_reg_loaded),
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self.data.d.eq(data_reg)
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]
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self.sync += [
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If(self.data.ack, data_reg_loaded.eq(0)),
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If(self.bus.ack,
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data_reg_loaded.eq(1),
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data_reg.eq(self.bus.dat_r)
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)
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]
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class Writer(Module):
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def __init__(self):
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self.bus = wishbone.Interface()
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self.address_data = Sink([("a", 30), ("d", 32)])
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self.busy = Signal()
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###
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self.comb += [
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self.busy.eq(0),
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self.bus.we.eq(1),
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self.bus.cyc.eq(self.address_data.stb),
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self.bus.stb.eq(self.address_data.stb),
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self.bus.adr.eq(self.address_data.a),
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self.bus.sel.eq(0xf),
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self.bus.dat_w.eq(self.address_data.d),
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self.address_data.ack.eq(self.bus.ack)
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]
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