203 lines
4.8 KiB
Python
203 lines
4.8 KiB
Python
from migen.fhdl import structure as f
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def log2_int(n, need_pow2=True):
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l = 1
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r = 0
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while l < n:
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l *= 2
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r += 1
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if need_pow2 and l != n:
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raise ValueError("Not a power of 2")
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return r
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def bits_for(n, require_sign_bit=False):
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if n > 0:
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r = log2_int(n + 1, False)
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else:
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require_sign_bit = True
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r = log2_int(-n, False)
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if require_sign_bit:
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r += 1
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return r
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def value_bits_sign(v):
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if isinstance(v, bool):
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return 1, False
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elif isinstance(v, int):
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return bits_for(v), v < 0
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elif isinstance(v, f.Signal):
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return v.nbits, v.signed
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elif isinstance(v, (f.ClockSignal, f.ResetSignal)):
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return 1, False
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elif isinstance(v, f._Operator):
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obs = list(map(value_bits_sign, v.operands))
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if v.op == "+" or v.op == "-":
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if not obs[0][1] and not obs[1][1]:
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# both operands unsigned
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return max(obs[0][0], obs[1][0]) + 1, False
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elif obs[0][1] and obs[1][1]:
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# both operands signed
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return max(obs[0][0], obs[1][0]) + 1, True
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elif not obs[0][1] and obs[1][1]:
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# first operand unsigned (add sign bit), second operand signed
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return max(obs[0][0] + 1, obs[1][0]) + 1, True
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else:
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# first signed, second operand unsigned (add sign bit)
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return max(obs[0][0], obs[1][0] + 1) + 1, True
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elif v.op == "*":
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if not obs[0][1] and not obs[1][1]:
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# both operands unsigned
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return obs[0][0] + obs[1][0]
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elif obs[0][1] and obs[1][1]:
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# both operands signed
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return obs[0][0] + obs[1][0] - 1
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else:
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# one operand signed, the other unsigned (add sign bit)
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return obs[0][0] + obs[1][0] + 1 - 1
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elif v.op == "<<<":
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if obs[1][1]:
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extra = 2**(obs[1][0] - 1) - 1
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else:
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extra = 2**obs[1][0] - 1
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return obs[0][0] + extra, obs[0][1]
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elif v.op == ">>>":
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if obs[1][1]:
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extra = 2**(obs[1][0] - 1)
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else:
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extra = 0
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return obs[0][0] + extra, obs[0][1]
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elif v.op == "&" or v.op == "^" or v.op == "|":
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if not obs[0][1] and not obs[1][1]:
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# both operands unsigned
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return max(obs[0][0], obs[1][0]), False
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elif obs[0][1] and obs[1][1]:
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# both operands signed
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return max(obs[0][0], obs[1][0]), True
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elif not obs[0][1] and obs[1][1]:
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# first operand unsigned (add sign bit), second operand signed
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return max(obs[0][0] + 1, obs[1][0]), True
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else:
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# first signed, second operand unsigned (add sign bit)
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return max(obs[0][0], obs[1][0] + 1), True
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elif v.op == "<" or v.op == "<=" or v.op == "==" or v.op == "!=" \
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or v.op == ">" or v.op == ">=":
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return 1, False
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elif v.op == "~":
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return obs[0]
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else:
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raise TypeError
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elif isinstance(v, f._Slice):
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return v.stop - v.start, value_bits_sign(v.value)[1]
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elif isinstance(v, f.Cat):
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return sum(value_bits_sign(sv)[0] for sv in v.l), False
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elif isinstance(v, f.Replicate):
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return (value_bits_sign(v.v)[0])*v.n, False
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elif isinstance(v, f._ArrayProxy):
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bsc = list(map(value_bits_sign, v.choices))
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return max(bs[0] for bs in bsc), any(bs[1] for bs in bsc)
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else:
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raise TypeError("Can not calculate bit length of {} {}".format(
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type(v), v))
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def flen(v):
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"""Bit length of an expression
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Parameters
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----------
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v : int, bool or Value
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Returns
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-------
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int
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Number of bits required to store `v` or available in `v`
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Examples
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--------
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>>> flen(f.Signal(8))
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8
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>>> flen(0xaa)
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8
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"""
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return value_bits_sign(v)[0]
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def fiter(v):
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"""Bit iterator
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Parameters
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----------
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v : int, bool or Value
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Returns
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-------
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iter
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Iterator over the bits in `v`
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Examples
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--------
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>>> list(fiter(f.Signal(2))) #doctest: +ELLIPSIS
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[<migen.fhdl.structure._Slice object at 0x...>, <migen.fhdl.structure._Slice object at 0x...>]
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>>> list(fiter(4))
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[0, 0, 1]
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"""
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if isinstance(v, (bool, int)):
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return ((v >> i) & 1 for i in range(bits_for(v)))
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elif isinstance(v, f.Value):
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return (v[i] for i in range(flen(v)))
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else:
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raise TypeError("Can not bit-iterate {} {}".format(type(v), v))
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def fslice(v, s):
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"""Bit slice
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Parameters
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----------
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v : int, bool or Value
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s : slice or int
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Returns
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-------
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int or Value
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Expression for the slice `s` of `v`.
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Examples
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--------
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>>> fslice(f.Signal(2), 1) #doctest: +ELLIPSIS
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<migen.fhdl.structure._Slice object at 0x...>
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>>> bin(fslice(0b1101, slice(1, None, 2)))
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'0b10'
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>>> fslice(-1, slice(0, 4))
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1
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>>> fslice(-7, slice(None))
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9
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"""
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if isinstance(v, (bool, int)):
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if isinstance(s, int):
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s = slice(s)
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idx = range(*s.indices(bits_for(v)))
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return sum(((v >> i) & 1) << j for j, i in enumerate(idx))
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elif isinstance(v, f.Value):
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return v[s]
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else:
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raise TypeError("Can not bit-slice {} {}".format(type(v), v))
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def freversed(v):
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"""Bit reverse
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Parameters
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----------
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v : int, bool or Value
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Returns
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-------
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int or Value
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Expression containing the bit reversed input.
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Examples
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--------
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>>> freversed(f.Signal(2)) #doctest: +ELLIPSIS
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<migen.fhdl.structure.Cat object at 0x...>
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>>> bin(freversed(0b1011))
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'0b1101'
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"""
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return fslice(v, slice(None, None, -1))
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